公开(公告)号：US11201162B2

公开(公告)日：2021-12-14

申请号：US16230048

申请日：2018-12-21

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: H01L27/00 ,  H01L27/11558 ,  H01L27/11526 ,  G11C16/04 ,  H01L27/11573

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

公开(公告)号：US09117518B2

公开(公告)日：2015-08-25

申请号：US13724623

申请日：2012-12-21

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: G11C14/00 ,  G11C19/28

CPC classification number: G11C16/14 ,  G11C14/00 ,  G11C14/0054 ,  G11C14/0063 ,  G11C19/28

Abstract: Non-Volatile Register (NVR) and Non-Volatile Shift Register (NVSR) devices are disclosed. The innovative NVR and NVSR devices of the invention can rapidly load the stored non-volatile data in non-volatile memory elements into their correspondent static memory elements for fast and constant referencing in digital circuitry. According to the invention, the loading process from non-volatile memory to static memory is a direct process without going through the conventional procedures of accessing the non-volatile memory, sensing from the non-volatile memory, and loading into the digital registers and shift registers.

Abstract translation: 公开了非易失性寄存器（NVR）和非易失性移位寄存器（NVSR）器件。 本发明的创新的NVR和NVSR设备可以将非易失性存储器元件中存储的非易失性数据快速加载到其对应的静态存储器元件中，以在数字电路中快速和恒定地引用。 根据本发明，从非易失性存储器到静态存储器的加载过程是直接的过程，而不需要经历访问非易失性存储器的常规过程，从非易失性存储器的感测和加载到数字寄存器中并且移位 注册

公开(公告)号：US08730723B2

公开(公告)日：2014-05-20

申请号：US13417655

申请日：2012-03-12

Applicant: Lee Wang

Inventor： Lee Wang

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C16/06 ,  G11C16/26

Abstract: Structures and methods of converting Multi-Level Cell (MLC) Non-Volatile Memory (NVM) into multi-bit information are disclosed. In MLC NVM system, multi-bit information stored in NVM cell is represented by the states of NVM cell threshold voltage levels. In this disclosure, “P” states of NVM cell threshold voltage levels are divided into “N” groups of threshold voltage levels. Each group contains “M” states of multiple threshold voltage levels of NVM cells, where P=N×M. The “M” states of NVM cell threshold voltage levels in each group are sensed and resolved by applying one correspondent gate voltage to the group. By applying “N” multiple gate voltages, the whole “P” states of NVM cell threshold voltage levels can be sensed and efficiently converted into storing bits in the MLC NVM cells.

Abstract translation: 公开了将多级单元（MLC）非易失性存储器（NVM）转换为多位信息的结构和方法。 在MLC NVM系统中，存储在NVM单元中的多位信息由NVM单元阈值电压电平的状态表示。 在本公开中，NVM单元阈值电压电平的“P”状态被分为阈值电压电平的“N”组。 每组包含NVM单元的多个阈值电压电平的“M”状态，其中P = N×M。 通过向组中施加一个对应的栅极电压来感测和解析每组中的NVM单元阈值电压电平的“M”状态。 通过施加“N”个多个栅极电压，可以感测NVM单元阈值电压电平的整个“P”状态并有效地转换成MLC NVM单元中的存储位。

公开(公告)号：US07606069B2

公开(公告)日：2009-10-20

申请号：US12113117

申请日：2008-04-30

Applicant: Lee Wang

Inventor： Lee Wang

IPC: G11C16/04

CPC classification number: G11C7/06 ,  G11C7/16 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28

Abstract: Storage of information represented by a multi-bit word in a single non-volatile memory cell is made possible by programming the threshold voltage of the non-volatile memory to a specific threshold level corresponding to the multi-bit word. Stored or generated multi-bit words are scanned and converted into a gate voltage to be applied to the non-volatile memory cell until the electrical response from the non-volatile memory cell indicates that the voltage generated from the specific multi-bit word which has been applied to the gate matches the information stored in the non-volatile memory cell. The matched multi-bit word is read out of storage and represents the stored bits in the single non-volatile memory cell.

Abstract translation: 通过将非易失性存储器的阈值电压编程到与多位字对应的特定阈值电平，可以将由多位字表示的信息存储在单个非易失性存储单元中。 扫描存储或生成的多位字，并将其转换为施加到非易失性存储器单元的栅极电压，直到来自非易失性存储单元的电响应指示从具有多个位的特定多位字产生的电压 被施加到门匹配存储在非易失性存储单元中的信息。 匹配的多位字从存储器读出，并表示单个非易失性存储器单元中存储的位。

公开(公告)号：US11662980B2

公开(公告)日：2023-05-30

申请号：US16675554

申请日：2019-11-06

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: G06F7/523 ,  G06F7/50 ,  G11C8/10 ,  G06F1/03 ,  G06F7/505

CPC classification number: G06F7/523 ,  G06F1/03 ,  G06F7/50 ,  G06F7/5057 ,  G11C8/10

Abstract: In-memory arithmetic processors for the “n-bit” by “n-bit” multiplication, the “n-bit” by “n-bit” addition, and the “n-bit” by “n-bit” subtraction operations are disclosed. The in-memory arithmetic processors of the invention can obtain the operational resultant integer in the binary format for two inputted integers represented by two “n-bit” binary codes in one-step processing with no sequential multiple-step operations as for the conventional arithmetic binary processors. The in-memory arithmetic processors are implemented by a 2-dimensional memory array with X and Y decoding for the two inputted operational integers in the arithmetic binary operations.

公开(公告)号：US11200029B2

公开(公告)日：2021-12-14

申请号：US16850825

申请日：2020-04-16

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: G06F7/507 ,  G06F7/50 ,  G11C8/08

Abstract: The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.

公开(公告)号：US10148254B2

公开(公告)日：2018-12-04

申请号：US15405747

申请日：2017-01-13

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: G11C5/14 ,  H03K3/012 ,  H03K3/356 ,  G11C11/412 ,  G11C11/417 ,  G11C11/419

Abstract: The standby leakage current reduction schemes for digital data storing components are disclosed. By floating the low digital voltage node of the digital data storing components in standby mode, the major standby leakage current paths to the ground voltage caused by the channel diffusion leakage current of MOSFET devices can be terminated. The standby leakage currents will be reduced to the small reverse junction leakage currents to the grounded substrate. For retaining the stored data in the digital data storing components in standby mode, the low digital voltage node is connected to the ground voltage periodically according to a plurality of rectangular voltage pulses outputted from a pulse generator trigged by a low frequency clock oscillator. Due to no external voltage bias to the low digital voltage node other than floating the digital low voltage node, the data recovering process is instant.

公开(公告)号：US09754668B1

公开(公告)日：2017-09-05

申请号：US15059733

申请日：2016-03-03

Applicant: FlashSilicon Incorporation

Inventor： Lee Wang

IPC: G11C15/04 ,  G11C7/22 ,  G11C5/06 ,  G06F12/1027 ,  G06F12/10 ,  G11C15/00 ,  G06F12/1036

CPC classification number: G11C7/22 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G11C11/005 ,  G11C11/54 ,  G11C13/0002 ,  G11C15/00 ,  G11C15/04 ,  G11C15/046

Abstract: In view of the neural network information parallel processing, a digital perceptron device analogous to the build-in neural network hardware systems for parallel processing digital signals directly by the processor's memory content and memory perception in one feed-forward step is disclosed. The digital perceptron device of the invention applies the configurable content and perceptive non-volatile memory arrays as the memory processor hardware. The input digital signals are then broadcasted into the non-volatile content memory array for a match to output the digital signals from the perceptive non-volatile memory array as the content-perceptive digital perceptron device.

公开(公告)号：US09595330B2

公开(公告)日：2017-03-14

申请号：US15283802

申请日：2016-10-03

Applicant: FLASHSILICON INCORPORATION

Inventor： Lee Wang

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: A Configurable Non-Volatile Content Addressable Memory (CNVCAM) cell consisting of a pair of complementary non-volatile memory devices and a MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) is disclosed. The CNVCAM cells can be constructed to form the NOR-type match line memory array and the NAND-type match line memory array. In contrast to the Random Access Memory (RAM) accessed by the address codes with the prior knowledge of memory locations, CNVCAM can be pre-configured into non-volatile memory content data and searched by an input content data to trigger the further computing process. The unique property of CNVCAM can provide a key component for neural computing.

Abstract translation: 公开了一种由一对互补非易失性存储器件和MOSFET（金属氧化物半导体场效应晶体管）组成的可配置非易失性内容可寻址存储器（CNVCAM）单元。 可以构造CNVCAM单元以形成NOR型匹配线存储器阵列和NAND型匹配线存储器阵列。 与通过存储器位置的先​​前知识的地址码访问的随机存取存储器（RAM）相反，CNVCAM可以被预先配置成非易失性存储器内容数据，并通过输入内容数据进行搜索以触发进一步的计算过程。 CNVCAM的独特属性可以为神经计算提供关键组件。

公开(公告)号：US09082490B2

公开(公告)日：2015-07-14

申请号：US13920886

申请日：2013-06-18

Applicant: FLASHSILICON INCORPORATION

Inventor： Lee Wang

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0466

Abstract: An Ultra-low power programming method for N-channel semiconductor Non-Volatile Memory (NVM) is disclosed. In contrast to the grounded voltage at the source electrode of an N-channel semiconductor NVM for the conventional Channel Hot Electron Injection (CHEI) programming, the source electrode in the programming method of the invention is necessarily floating with no voltage bias to prevent applied electrical fields toward the source electrode. The drain electrode of the N-channel semiconductor NVM is reversely biased with a positive voltage VDB relative to the substrate to facilitate the valence band electrons in the P-type substrate to tunnel to the conducting band of the N-type drain electrode. A positive high gate voltage pulse is then applied to the gate electrode of the N-channel semiconductor NVM to collect the surface energetic electrons toward the charge storage material.

Abstract translation: 公开了一种用于N沟道半导体非易失性存储器（NVM）的超低功率编程方法。 与用于常规通道热电子注入（CHEI）编程的N沟道半导体NVM的源极处的接地电压相反，本发明的编程方法中的源电极必然浮动，没有电压偏置以防止施加的电 场向源电极。 N沟道半导体NVM的漏电极相对于衬底以正电压VDB反向偏置，以便于P型衬底中的价带电子隧穿至N型漏电极的导带。 然后将正高栅极电压脉冲施加到N沟道半导体NVM的栅电极，以将表面能量电子收集到电荷存储材料。