公开(公告)号：US11714650B2

公开(公告)日：2023-08-01

申请号：US17709486

申请日：2022-03-31

Applicant: FUJITSU LIMITED

Inventor： Hiroki Tokura ,  Masato Nakagawa ,  Tomotake Nakamura

IPC: G06F9/30 ,  G06F9/32 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/30152 ,  G06F9/30043 ,  G06F9/30065 ,  G06F9/324 ,  G06F11/3471 ,  G06F11/3604

Abstract: The present disclosure relates to a non-transitory computer-readable recording medium storing an analysis program that causes a computer to execute a process. The process includes sampling an instruction address of one of instructions included in a program during execution of the program, identifying a first function that includes the sampled instruction address in an address range, rewriting mark information associated with the identified first function, identifying first information corresponding to the instruction address of the first function among a plurality of first information based on the rewritten mark information, identifying second information corresponding to the instruction address of the first function among a plurality of second information based on the rewritten mark information, storing the first information and the second information in a memory, and analyzing performance of the program based on the first information and the second information stored in the memory.

公开(公告)号：US10025589B2

公开(公告)日：2018-07-17

申请号：US15228067

申请日：2016-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dan F. Greiner ,  Christian Jacobi ,  Marcel Mitran ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3005 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30152 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/467

Abstract: A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

公开(公告)号：US09152421B2

公开(公告)日：2015-10-06

申请号：US13333918

申请日：2011-12-21

Applicant: Peter Smith ,  David Richard Hargreaves

Inventor： Peter Smith ,  David Richard Hargreaves

IPC: G06F9/30

CPC classification number: G06F9/30152 ,  G06F9/3017 ,  G06F9/30185

Abstract: A method of encapsulating a long instruction in a set of short instructions for execution on a processor, the long instruction having k bits and each short instruction having l bits where l

Abstract translation: 一种将长指令封装在一组用于在处理器上执行的短指令的方法，具有k位的长指令和每个具有l位的短指令，其中l

公开(公告)号：US08898437B2

公开(公告)日：2014-11-25

申请号：US11934108

申请日：2007-11-02

Applicant: Rodney Wayne Smith ,  Brian Michael Stempel ,  David John Mandzak ,  James Norris Dieffenderfer

Inventor： Rodney Wayne Smith ,  Brian Michael Stempel ,  David John Mandzak ,  James Norris Dieffenderfer

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30152 ,  G06F9/3816 ,  G06F9/382

Abstract: A predecode repair cache is described in a processor capable of fetching and executing variable length instructions having instructions of at least two lengths which may be mixed in a program. An instruction cache is operable to store in an instruction cache line instructions having at least a first length and a second length, the second length longer than the first length. A predecoder is operable to predecode instructions fetched from the instruction cache that have invalid predecode information to form repaired predecode information. A predecode repair cache is operable to store the repaired predecode information associated with instructions of the second length that span across two cache lines in the instruction cache. Methods for filling the predecode repair cache and for executing an instruction that spans across two cache lines are also described.

Abstract translation: 在能够获取和执行具有至少两个长度的指令的可变长度指令的处理器中描述了预代码修复高速缓存，其可以在程序中混合。 指令高速缓存用于存储指令高速缓存行指令，该指令具有至少第一长度和第二长度，第二长度长于第一长度。 预解码器可用于对具有无效预解码信息的指令高速缓存取出的指令进行预解码，以形成修复的预解码信息。 预解码修复高速缓存可操作用于存储与跨越指令高速缓存中的两个高速缓存行的第二长度的指令相关联的修复的预解码信息。 还描述了用于填充预解码修复高速缓存和用于执行跨越两个高速缓存行的指令的方法。

公开(公告)号：US20120324207A1

公开(公告)日：2012-12-20

申请号：US13333918

申请日：2011-12-21

Applicant: Peter Smith ,  David Richard Hargreaves

Inventor： Peter Smith ,  David Richard Hargreaves

IPC: G06F9/318

CPC classification number: G06F9/30152 ,  G06F9/3017 ,  G06F9/30185

Abstract: A method of encapsulating a long instruction in a set of short instructions for execution on a processor, the long instruction having k bits and each short instruction having l bits where l

Abstract translation: 一种将长指令封装在一组用于在处理器上执行的短指令的方法，具有k位的长指令和每个具有l位的短指令，其中l

公开(公告)号：US08335910B2

公开(公告)日：2012-12-18

申请号：US12572024

申请日：2009-10-01

Applicant: Thomas C. McDonald

Inventor： Thomas C. McDonald

IPC: G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/382 ,  G06F12/0862 ,  G06F2212/6028

Abstract: An apparatus extracts instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decoders generate an associated start/end mark for each instruction byte of a line from a first queue of entries each storing a line of instruction bytes. A second queue has entries each storing a line received from the first queue along with the associated start/end marks. Control logic detects a condition where the length of an instruction whose initial portion within a first line in the first queue is yet undeterminable because the instruction's remainder resides in a second line yet to be loaded into the first queue from the instruction cache; loads the first line and corresponding start/end marks into the second queue and refrains from shifting the first line out of the first queue, in response to detecting the condition; and extracts instructions from the first line in the second queue based on the corresponding start/end marks. The instructions exclude the yet undeterminable length instruction.

Abstract translation: 一种装置在具有其中指令是可变长度的指令集架构的微处理器中从未分化指令字节流中提取指令。 解码器从存储指令字节行的第一个条目队列生成一行的每个指令字节的相关起始/终止标记。 第二队列具有各自存储从第一队列接收的线以及相关联的开始/结束标记的条目。 控制逻辑检测其中在第一队列中的第一行内的初始部分尚未确定的指令的长度的条件，因为指令的余数驻留在尚未从指令高速缓存加载到第一队列中的第二行; 响应于检测到所述条件，将所述第一行和对应的开始/结束标记加载到所述第二队列中并且避免将所述第一行移出所述第一队列; 并基于相应的开始/结束标记从第二队列中的第一行提取指令。 该指令排除了尚未确定的长度指令。

公开(公告)号：US20120144168A1

公开(公告)日：2012-06-07

申请号：US12962113

申请日：2010-12-07

Applicant: Mike Butler ,  Donald A. Priore ,  Steven Beigelmacher

Inventor： Mike Butler ,  Donald A. Priore ,  Steven Beigelmacher

IPC: G06F9/30

CPC classification number: G06F9/30152 ,  G06F9/382

Abstract: A method and apparatus is presented for identifying instructions in a stream of information by preprocessing the stream of information, creating a vector of instructions and breaking the vector of instructions into two or more vectors for picking the identified instructions at a high frequency.

Abstract translation: 提供了一种用于通过预处理信息流来识别信息流中的指令的方法和装置，创建指令向量并将指令向量分解成两个或更多个向量，用于以高频率挑选所识别的指令。

公开(公告)号：US07823142B2

公开(公告)日：2010-10-26

申请号：US11245357

申请日：2005-10-07

Applicant: Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

Inventor： Shuichi Takayama ,  Hajime Ogawa ,  Kenichi Kawaguchi ,  Nobuo Higaki ,  Kensuke Odani ,  Tetsuya Tanaka ,  Shinya Miyaji ,  Taketo Heishi

IPC: G06F9/45

CPC classification number: G06F9/3802 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30167 ,  G06F9/321 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3822 ,  G06F9/3853

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract translation: 当指令解码器409a至409c解码分支指令时，分支指令中包括的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。 下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。 上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

公开(公告)号：US20080256338A1

公开(公告)日：2008-10-16

申请号：US11735567

申请日：2007-04-16

Applicant: David Neal Suggs

Inventor： David Neal Suggs

IPC: G06F9/30

CPC classification number: G06F9/3802 ,  G06F9/30152 ,  G06F9/30156 ,  G06F9/3017 ,  G06F9/30178 ,  G06F9/3806 ,  G06F9/382 ,  G06F9/3844

Abstract: A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information. The first decompressor is configured to decode at least some of the instruction bytes stored in the second memory to convert the combined predecode/branch information into second predecode information, which corresponds to an uncompressed version of the first predecode information, for storage in the third memory.

Abstract translation: 存储器子系统包括第一存储器，第二存储器，第一压缩器和第一解压缩器。 第一存储器被配置为存储取出窗口的指令字节，并且存储表征提取窗口的指令字节的第一预解码信息和第一分支信息。 第二存储器被配置为在从第一存储器消除指令字节并存储也表征获取窗口的指令字节的组合预解码/转移信息时，存储取指示窗口的指令字节。 第一压缩器被配置为将第一预解码信息和第一分支信息压缩成组合的预解码/分支信息。 第一解压缩器被配置为对存储在第二存储器中的至少一些指令字节进行解码，以将组合的预解码/转移信息转换成对应于第一预解码信息的未压缩版本的第二预解码信息，以存储在第三存储器中 。

公开(公告)号：US07415638B2

公开(公告)日：2008-08-19

申请号：US10995858

申请日：2004-11-22

Applicant: Rodney Wayne Smith ,  Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

Inventor： Rodney Wayne Smith ,  Brian Michael Stempel ,  James Norris Dieffenderfer ,  Jeffrey Todd Bridges ,  Thomas Andrew Sartorius

IPC: G06F11/00 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30152 ,  G06F9/3017 ,  G06F9/382

Abstract: In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.

Abstract translation: 在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。 相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。 特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。 这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。 然后重新获取的指令被正确预解码，写入高速缓存并执行。