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37 条记录 (耗时 0.012 秒)

    Programmable gate array (FPGA) for realizing external monitoring and configuration
    1.
    发明授权
    Programmable gate array (FPGA) for realizing external monitoring and configuration 有权

    公开(公告)号：US12095460B2

    公开(公告)日：2024-09-17

    申请号：US17955578

    申请日：2022-09-29

    申请人： WUXI ESIONTECH CO., LTD.

    发明人： Yueer Shan ,  Zhengzhou Cao ,  Wenhu Xie ,  Yanfei Zhang ,  Ting Jiang ,  Bo Tu

    IPC分类号： H03K19/20 ,  H03K19/17748

    CPC分类号： H03K19/17748 ,  H03K19/20

    摘要： A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.

    Programmable logic circuit device and image processing apparatus
    2.
    发明授权
    Programmable logic circuit device and image processing apparatus 有权

    公开(公告)号：US12057835B2

    公开(公告)日：2024-08-06

    申请号：US17315387

    申请日：2021-05-10

    申请人： FUJIFILM Business Innovation Corp.

    发明人： Fumiaki Sugiyama

    IPC分类号： H03K19/177 ,  H03K19/173 ,  H03K19/17748

    CPC分类号： H03K19/17748 ,  H03K19/1733

    摘要： A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements. The processor is configured to: upon detection of an abnormality while performing processing in a state in which the elements in the reconfiguration regions are connected in accordance with reconfiguration data designating connection between the elements in the reconfiguration regions, acquire reconfiguration data designating such connection between the elements that the processing being performed is not performed; and change connection between the elements in the reconfiguration regions in accordance with the designation by the acquired reconfiguration data.

    CONFIGURATION CIRCUIT OF FLASH FIELD PROGRAMMABLE GATE ARRAY (FPGA) FOR REALIZING EXTERNAL MONITORING AND CONFIGURATION
    3.
    发明申请
    CONFIGURATION CIRCUIT OF FLASH FIELD PROGRAMMABLE GATE ARRAY (FPGA) FOR REALIZING EXTERNAL MONITORING AND CONFIGURATION 有权

    公开(公告)号：US20230020524A1

    公开(公告)日：2023-01-19

    申请号：US17955578

    申请日：2022-09-29

    申请人： WUXI ESIONTECH CO., LTD.

    发明人： Yueer SHAN ,  Zhengzhou CAO ,  Wenhu XIE ,  Yanfei ZHANG ,  Ting JIANG ,  Bo TU

    IPC分类号： H03K19/17748 ,  H03K19/20

    摘要： A configuration circuit of a flash FPGA for realizing external monitoring and configuration is provided. In the configuration circuit, a positive high-voltage output terminal of a positive high-voltage charge pump is connected to a positive high-voltage external monitoring port through a positive high-voltage bidirectional switch circuit, and the positive high-voltage output terminal of a positive high-voltage charge pump is further configured as a positive output end of a voltage supply circuit. A negative high-voltage output terminal of a negative high-voltage charge pump is connected to a negative high-voltage external monitoring port through a negative high-voltage bidirectional switch circuit, and the negative high-voltage output terminal of a negative high-voltage charge pump is further configured as a negative output end of the voltage supply circuit. Based on a received mode adjustment signal, a mode control circuit controls to enter an external monitoring mode or an external configuration mode.

    Dual-mode operation of application specific integrated circuits
    5.
    发明授权
    Dual-mode operation of application specific integrated circuits 有权

    公开(公告)号：US11811401B2

    公开(公告)日：2023-11-07

    申请号：US17634744

    申请日：2020-08-14

    申请人： Google LLC

    发明人： Reiner Pope

    IPC分类号： H03K19/17736 ,  G06N3/063 ,  H03K19/17748

    CPC分类号： H03K19/1774 ,  G06N3/063 ,  H03K19/17748

    摘要： A method for operating an integrated circuit chip including multiple tiles (202a-202d) includes determining a configuration for the tiles for execution of a computation. When the configuration for the tiles satisfies a first criterion, the integrated circuit is operated in a first mode, including concurrently receiving respective input data (208a, 208b) at each of the tiles (202a-202d). When the configuration for the tiles satisfies a second criterion, the integrated circuit is operated in a second mode, including: at a first time, concurrently receiving respective first input data (208a, 208b) at each tile (202a, 202b) of a first group of tiles; at the first time, storing respective second input data (208a, 208b) in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile (202c, 202d) of a second group of tiles; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles.

    FPGA Specialist Processing Block for Machine Learning
    6.
    发明申请
    FPGA Specialist Processing Block for Machine Learning 有权

    公开(公告)号：US20210182023A1

    公开(公告)日：2021-06-17

    申请号：US16914107

    申请日：2020-06-26

    申请人： Intel Corporation

    发明人： Martin Langhammer ,  Dongdong Chen ,  Jason R. Bergendahl

    IPC分类号： G06F7/523 ,  G06F7/50 ,  G06N20/00 ,  H03M7/24 ,  H03K19/17748

    摘要： The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.

    Information processing apparatus and information processing method for process order in reconfigurable circuit
    7.
    发明授权
    Information processing apparatus and information processing method for process order in reconfigurable circuit 有权

    公开(公告)号：US10754817B2

    公开(公告)日：2020-08-25

    申请号：US16032101

    申请日：2018-07-11

    申请人： FUJITSU LIMITED

    发明人： Toshiyuki Ichiba

    IPC分类号： G06F15/78 ,  G06F17/50 ,  H03K19/177 ,  H03K19/17736 ,  H03K19/17748 ,  G06F30/34

    摘要： An information processing apparatus having a reconfigurable circuit capable of rewriting a logic circuit includes, a process determination circuit that determines which of a plurality of processes is to be executed, a standby buffer circuit that holds process data to be used in a process waiting for execution among processes determined by the process determination circuit, and a rewrite control circuit that rewrites the current logic circuit written in the reconfigurable circuit to a logic circuit that executes one of the plurality of processes waiting for execution using each of a plurality of process data held in the standby buffer circuit when the amount of process data held in the standby buffer circuit exceeds a first predetermined amount.

    Programmable logic circuit device and image processing apparatus
    9.
    发明授权
    Programmable logic circuit device and image processing apparatus 有权

    公开(公告)号：US12040796B2

    公开(公告)日：2024-07-16

    申请号：US17314060

    申请日：2021-05-07

    申请人： FUJIFILM Business Innovation Corp.

    发明人： Fumiaki Sugiyama

    IPC分类号： H03K19/1776 ,  H03K19/17748 ,  H04N1/00 ,  H04N1/23

    CPC分类号： H03K19/17748 ,  H04N1/00954 ,  H04N1/0097 ,  H04N1/2307

    摘要： A programmable logic circuit device includes: a processor; and plural reconfiguration regions each including a circuit configured by change of connection between elements, wherein the processor is configured to: receive designation of a processing group including a series of plural kinds of processing; acquire management data decided for each processing group, the management data designating plural pieces of reconfiguration data each designating connection between elements in a corresponding one of the plural reconfiguration regions so that the designated processing group is performed; acquire the plural pieces of reconfiguration data designated by the acquired management data; change connection between elements in the plural reconfiguration regions in accordance with the designation by the acquired plural pieces of reconfiguration data; and when connection between elements is changed in accordance with designation by the plural pieces of reconfiguration data, in a case where designation by at least one of the acquired plural pieces of reconfiguration data does not require change of connection in a corresponding one(s) of the plural reconfiguration regions, use same reconfiguration data as that used to connect the elements in the corresponding one(s) of the plural reconfiguration regions.