公开(公告)号：US5786253A

公开(公告)日：1998-07-28

申请号：US892025

申请日：1997-07-14

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8234

CPC分类号： H01L27/11233 ,  H01L27/112

摘要： A method of making multi-level ROM devices in which the gate width controls the threshold voltage setting of each memory unit, instead of the conventional method of setting the threshold voltage through the implantation of ions into the channel region of a memory unit. The memory units include memory units having their word line polysilicon layer completely removed, which are units in an OFF state. Memory units having part of the word line polysilicon layer removed are units with a higher threshold voltage, while memory units having the word line polysilicon layer left untouched are memory units with a lower threshold voltage.

摘要翻译： 制造多级ROM器件的方法，其中栅极宽度控制每个存储器单元的阈值电压设置，而不是通过将离子注入存储器单元的沟道区域来设置阈值电压的常规方法。 存储单元包括其字线多晶硅层完全去除的存储单元，它们是处于OFF状态的单元。 具有去除字线多晶硅层的一部分的存储单元是具有较高阈值电压的单元，而具有保持不变的字线多晶硅层的存储单元是具有较低阈值电压的存储单元。

公开(公告)号：US5783457A

公开(公告)日：1998-07-21

申请号：US807887

申请日：1997-02-26

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： H01L21/336 ,  H01L29/788 ,  H01L21/8247 ,  H01L21/265

CPC分类号： H01L29/66825 ,  H01L29/7883

摘要： A method of making a flash memory cell includes patterning a series of layers over a semiconductor substrate of a first conductivity type to form a gate electrode structure. A first ion implantation procedure is performed to introduce a first impurity of a second conductivity type into the semiconductor substrate and form a heavily-doped source region and a heavily-doped drain region. A second ion implantation procedure is performed at a tilt angle of 25.degree. to 45.degree., to introduce a second impurity of the second conductivity type into the semiconductor substrate and form a pair of asymmetric lightly-doped regions, with one of the asymmetric lightly-doped regions surrounding the heavily-doped source region, and the other of the asymmetric lightly-doped regions beneath the heavily-doped drain region. An insulating spacer is formed on sidewalls of the gate electrode structure. A photoresist layer is coated over exposed surfaces of the gate electrode structure, the insulating spacer, and the heavily-doped source region and drain region. The photoresist layer is patterned to form an opening and expose a portion of the gate electrode structure, the insulating spacer, and the heavily-doped drain region. The exposed portion of the insulating spacer is removed. A third ion implantation procedure is performed at a tilt angle of 25.degree. to 45.degree., to introduce an impurity of the first conductivity type into the semiconductor substrate and form a heavily-doped pocket region surrounding the heavily-doped drain region. The photoresist layer is then removed.

摘要翻译： 制造闪存单元的方法包括在第一导电类型的半导体衬底上图案化一系列层以形成栅电极结构。 执行第一离子注入程序以将第二导电类型的第一杂质引入半导体衬底并形成重掺杂源极区和重掺杂漏极区。 以25°〜45°的倾斜角进行第二离子注入工序，将第二导电型的第二杂质引入半导体衬底，形成一对不对称的轻掺杂区域， 围绕重掺杂源极区域的掺杂区域，以及重掺杂漏极区域下方的不对称轻掺杂区域中的另一个。 在栅电极结构的侧壁上形成绝缘间隔物。 在栅极电极结构，绝缘间隔物和重掺杂源极区域和漏极区域的暴露表面上涂覆光致抗蚀剂层。 图案化光致抗蚀剂层以形成开口并暴露出栅电极结构，绝缘间隔物和重掺杂漏极区的一部分。 去除绝缘间隔物的暴露部分。 以25°至45°的倾斜角度进行第三离子注入步骤，以将第一导电类型的杂质引入半导体衬底中，并形成围绕重掺杂漏极区的重掺杂袋状区域。 然后除去光致抗蚀剂层。

公开(公告)号：US5777486A

公开(公告)日：1998-07-07

申请号：US777119

申请日：1996-12-30

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： G01R31/28 ,  G01R1/04

CPC分类号： G01R31/2831

摘要： A test pattern simulates conductors and interconnections of conductors of a multi-layer semiconductor device that may be subject to damage from electromigration. Test pattern elements are connected in a series circuit with two connection points for applying a test current to the elements. A break in this circuit or an increase in resistance during the test signifies that electromigration has damaged the test pattern and that the operating components of the device may have manufacturing defects that make them susceptible to electromigration. Probe points can be provided for testing particular parts of the series circuit. The pattern has at least one conductive stripe or other element in each layer of the device and it has interconnecting vias between these elements through one or more intervening layers of insulation where corresponding layer-to-layer interconnections are made in the operating components of the device. On the surface of the device, diffusions form part of the circuit path. The diffusions can be connected as a buried contact if the device uses this structure.

摘要翻译： 测试图案模拟可能受到电迁移损害的多层半导体器件的导体的导体和互连。 测试图形元件连接在具有用于向元件施加测试电流的两个连接点的串联电路中。 该电路中的断路或测试期间的电阻增加表示电迁移已经损坏了测试图案，并且器件的操作部件可能具有使其易于电迁移的制造缺陷。 可以提供探针点来测试串联电路的特定部分。 该图案在器件的每层中具有至少一个导电条纹或其它元件，并且在这些元件之间通过一个或多个中间绝缘层具有互连通孔，其中相应的层间互连在器件的操作部件中形成 。 在器件的表面上，扩散形成电路路径的一部分。 如果设备使用这种结构，则扩散可以作为埋地接头连接。

公开(公告)号：US5763925A

公开(公告)日：1998-06-09

申请号：US835924

申请日：1997-04-10

申请人： Chen-Chung Hsu

发明人： Chen-Chung Hsu

IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C17/12

CPC分类号： H01L27/1128 ,  H01L27/112

摘要： A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers. A plurality of gate layers are located over the gate oxide layer and the silicon nitride layers and serve as word lines. A region between any two adjacent source/drain regions comprises a channel region.

公开(公告)号：US5763305A

公开(公告)日：1998-06-09

申请号：US784298

申请日：1997-01-16

申请人： Fang-Ching Chao

发明人： Fang-Ching Chao

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  Y10S148/014

摘要： A method of fabricating a semiconductor memory device having a capacitor. First, a first insulating layer is formed on a substrate to cover the transistor. Next, a second insulating layer and a first conductive layer are formed in order. The first conductive layer only covers a portion of the second insulating layer to form a branch-like conductive layer. Then, a third insulating layer is formed. An opening is next formed. A second conductive layer is filled into the opening and therefore electrically connected to the source/drain region of the transistor to form a trunk-like conductive layer. Next, the second and the third insulating layers are removed. After a dielectric film is formed on the exposed surfaces of the first and second conductive layers, a third conductive layer is formed on the dielectric film to form an opposed electrode.

摘要翻译： 一种制造具有电容器的半导体存储器件的方法。 首先，在基板上形成第一绝缘层以覆盖晶体管。 接下来，依次形成第二绝缘层和第一导电层。 第一导电层仅覆盖第二绝缘层的一部分以形成分支状导电层。 然后，形成第三绝缘层。 接下来形成一个开口。 第二导电层填充到开口中，因此电连接到晶体管的源极/漏极区域以形成树干状的导电层。 接下来，去除第二和第三绝缘层。 在第一和第二导电层的暴露表面上形成电介质膜之后，在该电介质膜上形成第三导电层以形成相对的电极。

公开(公告)号：US5750438A

公开(公告)日：1998-05-12

申请号：US658032

申请日：1996-06-04

申请人： Chen-Chiu Hsue ,  Sun-Chieh Chien

发明人： Chen-Chiu Hsue ,  Sun-Chieh Chien

IPC分类号： H01L21/768 ,  H01L21/283 ,  H01L21/306

CPC分类号： H01L21/76889

摘要： A local interconnection structure is disclosed. The local interconnection structure is formed on a silicon substrate in which a polysilicon gate and a number of diffusion regions exist. The structure includes a number of metal silicide layers over the substrate, a metal nitride layer over the silicide layers, and a dielectric layer over the nitride layer. The metal nitride layer which electrically connects the diffusion regions and the gate forms the interconnection. The method for fabricating the interconnection structure includes the steps of preparing the silicon substrate, sputtering a metal layer, annealing to form silicide and the nitride layers, depositing the dielectric layer, and patterning the nitride layer and the metal nitride by covering with a mask, etching away portions of both the dielectric layer and metal nitride layer not covered by the mask, and removing the mask after etching.

摘要翻译： 公开了局部互连结构。 局部互连结构形成在其中存在多晶硅栅极和多个扩散区域的硅衬底上。 该结构包括在衬底上的多个金属硅化物层，在硅化物层之上的金属氮化物层，以及氮化物层上方的电介质层。 电连接扩散区域和栅极的金属氮化物层形成互连。 制造互连结构的方法包括以下步骤：制备硅衬底，溅射金属层，退火以形成硅化物和氮化物层，沉积电介质层，以及用掩模覆盖来对氮化物层和金属氮化物进行图案化， 蚀刻除了未被掩模覆盖的电介质层和金属氮化物层的部分，以及蚀刻后去除掩模。

公开(公告)号：US5744847A

公开(公告)日：1998-04-28

申请号：US923547

申请日：1997-09-02

申请人： Jemmy Wen

发明人： Jemmy Wen

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L27/108 ,  H01L29/788 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/66636 ,  H01L21/823418 ,  H01L29/0653 ,  H01L29/0847 ,  Y10S257/903

摘要： This invention describes a device structure and a method of forming the device structure using trenches with sidewalls formed in the substrate of an integrated circuit. A highly doped polysilicon layer is formed on the walls of the trench or the trench is filled with highly doped polysilicon to form the source and drain of a field effect transistor in an integrated circuit. The invention provides reduced source and drain resistance. The capacitances between the gate and source and the gate and drain are reduced as well.

摘要翻译： 本发明描述了使用在集成电路的衬底中形成的具有侧壁的沟槽形成器件结构的器件结构和方法。 在沟槽的壁上形成高度掺杂的多晶硅层，或者沟槽中填充有高掺杂多晶硅以形成集成电路中的场效应晶体管的源极和漏极。 本发明提供了降低的源极和漏极电阻。 栅极和源极之间的电容以及栅极和漏极也被减小。

公开(公告)号：US5740580A

公开(公告)日：1998-04-21

申请号：US757679

申请日：1996-11-29

申请人： Chung-Chien Leu ,  Hsi-Huang Lee ,  En-Tien Tan

发明人： Chung-Chien Leu ,  Hsi-Huang Lee ,  En-Tien Tan

IPC分类号： B08B1/00 ,  G03F7/20 ,  H01L21/027 ,  H01L21/683 ,  A47L25/00

CPC分类号： G03F7/707 ,  B08B1/00 ,  G03F7/70866 ,  H01L21/6833

摘要： The present invention discloses a stepper vacuum chuck wiper for cleaning a stepper vacuum chuck, which includes a rod frame, a bearing device, a flare type soft shield, a wiping stick and an illuminating device. The rod frame has a through hole at one end and the bearing device is sleeved inside of the through hole. The flare type soft shield with a flare opening on its lower end is sleeved inside the bearing device, and the diameter of the flare opening is larger than the outside diameter of the bearing device. The wiping stick is sleeved inside the flare type soft shield. The illuminating device for illuminating the stepper vacuum chuck includes a light source, a battery set and a switch. The battery set is coupled to the other end of the rod frame to provide electricity to the light source, and the switch is coupled between the battery set and the light source to control the illumination of the light source, wherein the light source and the switch are disposed on the rod frame.

摘要翻译： 本发明公开了一种用于清洁步进真空吸盘的步进真空吸盘刮水器，其包括杆架，轴承装置，火炬式软护罩，擦拭棒和照明装置。 杆架在一端具有通孔，轴承装置套在通孔的内部。 在其下端具有喇叭口的喇叭型软护罩套在轴承装置的内部，喇叭口的直径大于轴承装置的外径。 擦拭棒套在Flare型软屏内。 用于照射步进真空吸盘的照明装置包括光源，电池组和开关。 电池组联接到杆框架的另一端以向光源提供电力，并且开关耦合在电池组和光源之间以控制光源的照明，其中光源和开关 设置在杆框架上。

公开(公告)号：US5740381A

公开(公告)日：1998-04-14

申请号：US577555

申请日：1995-12-22

申请人： Chih-Chan Yen

发明人： Chih-Chan Yen

IPC分类号： G06F13/364 ,  G06F13/00 ,  G06F13/36

CPC分类号： G06F13/364

摘要： An arbitration bus is arranged between a core logic chip set and a plurality of peripheral devices in order to arbitrate requests by the peripheral devices to use system memory of a computer system. Three or two arbitration signals carried on the arbitration bus. Means are provided to differentiate two levels of priority in each peripheral device. The core logic chip set can make a response pressing or otherwise so as to promote the overall performance. Preemption is provided so that peripheral devices can be overridden without wasting time when it is necessary to do so. Each peripheral device outputs a row address strobe (RAS) signal, all of which are connected together to form a open-collector signal to the core logic chip set for automatically accessing corresponding memory banks of system memory.

摘要翻译： 仲裁总线被布置在核心逻辑芯片组和多个外围设备之间，以便仲裁由外围设备使用计算机系统的系统存储器的请求。 在仲裁总线上承载三或两个仲裁信号。 提供了用于区分每个外围设备中的两个优先级的装置。 核心逻辑芯片组可以按照或其他方式做出响应，以提升整体性能。 提供抢占，以便外部设备可以在不需要浪费时间的情况下被覆盖。 每个外围设备输出行地址选通（RAS）信号，所有这些信号都连接在一起，以形成开放集电极信号到核心逻辑芯片组，用于自动访问系统存储器的相应存储器组。

公开(公告)号：US5738699A

公开(公告)日：1998-04-14

申请号：US706730

申请日：1996-09-06

申请人： Chu Lin Hu ,  Chia Hsing Huang ,  Ching Wen Deng ,  Kuo Cheng Chang

发明人： Chu Lin Hu ,  Chia Hsing Huang ,  Ching Wen Deng ,  Kuo Cheng Chang

IPC分类号： B01D5/00 ,  B01D7/02 ,  B01D47/06

CPC分类号： B01D7/02 ,  B01D47/06 ,  B01D5/0096

摘要： An apparatus for the removal of particles existing in exhaust gases by directly sprinkling the gases with water to congeal the particles. The apparatus also mixes surfactants into the water, and the mixture is driven by a pump to clean out the condensation deposited in a transmitting conduit in order to eliminate settled congealed particles that could block the transmitting conduit.

摘要翻译： 用于通过用水直接喷洒气体以凝结颗粒来除去废气中存在的颗粒的装置。 该设备还将表面活性剂混合到水中，并且混合物由泵驱动以清除沉积在传输导管中的冷凝物，以便消除可能堵塞传输导管的沉降的凝结颗粒。