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公开(公告)号：US11444631B2
公开(公告)日：2022-09-13
申请号：US16281047
申请日：2019-02-20
Applicant: Analog Devices, Inc.
Inventor： Ahmed Mohamed Abdelatty Ali
Abstract: Amplifiers can be found in pipelined ADCs and pipelined-SAR ADCs as inter-stage amplifiers. The amplifiers can in some cases implement and provide gains in high speed track and hold circuits. The amplifier structures can be open-loop amplifiers, and the amplifier structures can be used in MDACs and samplers of high speed ADCs. The amplifiers can be employed without resetting, and with incomplete settling, to maximize their speed and minimize their power consumption. The amplifiers can be calibrated to improve performance.
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公开(公告)号：US20220276290A1
公开(公告)日：2022-09-01
申请号：US17746577
申请日：2022-05-17
Applicant: Analog Devices, Inc.
Inventor： Isaac Chase NOVET , Steven J. DECKER
IPC: G01R27/26
Abstract: An impedance sensing circuit includes three impedance elements and a sensing element arranged in a bridge configuration. A first input terminal is coupled to two of the impedance elements to apply a stimulus signal. In a mutual-sensing mode, a second input terminal is coupled to the third impedance element and the sensing impedance element to apply an opposite phase stimulus signal. The impedance sensing circuit may be configured in a self-sensing mode, in which the opposite phase stimulus signal is decoupled from the third impedance element and the sensing impedance element. At least one of the impedance elements is variable and may be adjusted to balance an offset impedance load on the sensing element.
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公开(公告)号：US11423572B2
公开(公告)日：2022-08-23
申请号：US16664453
申请日：2019-10-25
Applicant: Analog Devices, Inc.
Inventor： Charles Mathy , Brian C. Donnelly , Nicolas Le Dortz , Sefa Demirtas
Abstract: An image processing system having on-the-fly calibration uses the placement of the imaging sensor and the light source for calibration. The placement of the imaging sensor and light source with respect to each other affect the amount of signal received by a pixel as a function of distance to a selected object. For example, an obstruction can block the light emitter, and as the obstruction is positioned an increasing distance away from the light emitter, the signal level increases as light rays leave the light emitters, bounce off the obstruction and are received by the imaging sensor. The system includes a light source configured to emit light, and an image sensor to collect incoming signals including reflected light, and a processor to determine a distance measurement at each of the pixels and calibrate the system.
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公开(公告)号：US11378689B2
公开(公告)日：2022-07-05
申请号：US16793505
申请日：2020-02-18
Applicant: Analog Devices, Inc.
Inventor： Tyler Adam Dunn , Andrew William Sparks , Michael Ziemkiewicz , Miles R. Bennett
IPC: G01C3/08 , G01S17/34 , G01S7/4914 , G01S7/4911
Abstract: A light detection and ranging (LIDAR) system comprises a laser diode; a laser diode driver circuit configured generate a laser beam using the laser diode and to frequency chirp the generated laser beam according to a frequency chirp period; a laser splitter to split the generated laser beam into N transmit laser beams pointed at different angles, wherein N is an integer greater than one, and a frequency chirp period of each of the N transmit laser beams is the frequency chirp period of the generated laser beam; and multiple return beam paths to receive N return beams and determine time of flight values for the N return beams in parallel.
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公开(公告)号：US20220173742A1
公开(公告)日：2022-06-02
申请号：US17454221
申请日：2021-11-09
Applicant: Analog Devices, Inc.
Inventor： Reuben P. Nelson
Abstract: Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and/or alignment to phase information lost in decimation.
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Patent Agency Ranking
公开(公告)号：US20220162059A1
公开(公告)日：2022-05-26
申请号：US17668326
申请日：2022-02-09
Applicant: Analog Devices, Inc.
Inventor： Charles Blackmer , Jeffrey A. Gregory , Nikolay Pokrovskiy , Bradley C. Kaanta
IPC: B81C1/00 , G01C19/5755 , G01P15/08
Abstract: Microelectromechanical system (MEMS) inertial sensors exhibiting reduced parasitic capacitance are described. The reduction in the parasitic capacitance may be achieved by forming localized regions of thick dielectric material. These localized regions may be formed inside trenches. Formation of trenches enables an increase in the vertical separation between a sense capacitor and the substrate, thereby reducing the parasitic capacitance in this region. The stationary electrode of the sense capacitor may be placed between the proof mass and the trench. The trench may be filled with a dielectric material. Part of the trench may be filled with air, in some circumstances, thereby further reducing the parasitic capacitance. These MEMS inertial sensors may serve, among other types of inertial sensors, as accelerometers and/or gyroscopes. Fabrication of these trenches may involve lateral oxidation, whereby columns of semiconductor material are oxidized.
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公开(公告)号：US11342930B2
公开(公告)日：2022-05-24
申请号：US17098724
申请日：2020-11-16
Applicant: Analog Devices, Inc.
Inventor： Ahmed Mohamed Abdelatty Ali
Abstract: A dither capacitor, separate from the capacitor sampling the input signal, can be used to inject the additive dither in the switched-capacitor network of the track and hold circuit. This implementation can be referred to as a split-capacitor dither injection. The dither capacitor can be connected to a summing node of the switched-capacitor network. Using a separate capacitor allows the dither to be isolated from the capacitor that is sampling the input signal and avoids kick-back errors.
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公开(公告)号：US11313903B2
公开(公告)日：2022-04-26
申请号：US17071609
申请日：2020-10-15
Applicant: Analog Devices, Inc.
Inventor： Amit Kumar Singh , Christopher C. McQuilkin , Brian Carey
IPC: G01R31/67 , G01R31/317 , G01R31/26 , G01R31/319
Abstract: A force-sense system can provide signals to, or receive signals from, a device under test (DUT) at a first DUT node. The system can include output buffer circuitry configured to provide a DUT signal to the DUT in response to a force control signal at a buffer control node, and controller circuitry configured to provide the force control signal at the buffer control node. The system can include bypass circuitry configured to selectively bypass the controller circuitry and provide an auxiliary control signal at the buffer control node. The auxiliary control signal can be used for system calibration. In an example, an external calibration circuit can provide the auxiliary control signal in response to information received from the DUT.
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公开(公告)号：US20220115955A1
公开(公告)日：2022-04-14
申请号：US17066128
申请日：2020-10-08
Applicant: Analog Devices, Inc.
Inventor： Yingyi Yan
Abstract: A switching converter circuit comprises an inductive circuit element; a driver switching circuit configured to provide energy to the inductive circuit element to generate an output voltage of the switching converter circuit, the output voltage having an alternating current (AC) signal component and a direct current (DC) signal component; a current sensing circuit configured to generate a current sense signal representative of inductor current of the inductive circuit element, wherein an output of the current sensing circuit is coupled to a bias circuit node; and a dynamic bias circuit configured to apply a dynamic bias voltage to the bias circuit node, wherein the dynamic bias voltage includes an AC component that tracks the AC signal component of the output voltage.
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公开(公告)号：US11303282B1
公开(公告)日：2022-04-12
申请号：US17382104
申请日：2021-07-21
Applicant: Analog Devices, Inc.
Inventor： John Kenney
Abstract: An apparatus is described and includes a current integrating phase interpolator core having a programmable bias current; an inverter circuit coupled to an output of the current integrating phase interpolator core for receiving a signal comprising a periodic sawtooth waveform therefrom; a digital-to-analog (D/A) converter for setting an input common mode voltage of the inverter circuit; a duty cycle measurement (DCM) circuit for measuring a duty cycle distortion (DCD) of a clock signal output from the inverter circuit; and a circuit for computing a difference between a first state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a high voltage and a second state of the DCD of the clock signal corresponding to the input common mode voltage of the inverter circuit being set to a low voltage.
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