公开(公告)号：US20090279989A1

公开(公告)日：2009-11-12

申请号：US12116897

申请日：2008-05-07

Applicant: Scott Wong ,  Jeffrey Lin ,  Andrew D. Bailey, III ,  Jack Chen ,  Benjamin W. Mooring ,  Chung Ho Huang

Inventor： Scott Wong ,  Jeffrey Lin ,  Andrew D. Bailey, III ,  Jack Chen ,  Benjamin W. Mooring ,  Chung Ho Huang

IPC: H01L21/67

CPC classification number: H01L21/68

Abstract: Methods and systems to optimize wafer placement repeatability in semiconductor manufacturing equipment using a controlled series of wafer movements are provided. In one embodiment, a preliminary station calibration is performed to teach a robot position for each station interfaced to facets of a vacuum transfer module used in semiconductor manufacturing. The method also calibrates the system to obtain compensation parameters that take into account the station where the wafer is to be placed, position of sensors in each facet, and offsets derived from performing extend and retract operations of a robot arm. In another embodiment where the robot includes two arms, the method calibrates the system to compensate for differences derived from using one arm or the other. During manufacturing, the wafers are placed in the different stations using the compensation parameters.

Abstract translation: 提供了使用受控系列的晶片移动来优化半导体制造设备中的晶片布置重复性的方法和系统。 在一个实施例中，执行初步站校准以教导与用于半导体制造中的真空传递模块的面连接的每个站的机器人位置。 该方法还校准系统以获得考虑要放置晶片的工位的位置的补偿参数，每个面中的传感器的位置以及执行机器人臂的延伸和缩回操作导出的偏移。 在机器人包括两个臂的另一实施例中，该方法校准系统以补偿从使用一个臂或另一个臂导出的差异。 在制造期间，使用补偿参数将晶片放置在不同的台中。

公开(公告)号：US20090114244A1

公开(公告)日：2009-05-07

申请号：US11758576

申请日：2007-06-05

Applicant: Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi

Inventor： Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi

IPC: C25F1/00

CPC classification number: H01L21/02087 ,  B08B7/0035 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32541 ,  H01L21/67069

Abstract: The embodiments provide structures and mechanisms for removal of etch byproducts, dielectric films and metal films on and near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a bottom electrode configured to receive the substrate, wherein the bottom electrode is coupled to a radio frequency (RF) power supply. The plasma processing chamber also includes a top edge electrode surrounding an insulating plate opposing the bottom electrode. The top edge electrode is electrically grounded. The plasma processing chamber further includes a bottom edge electrode surrounding the bottom electrode. The bottom edge electrode opposes the top edge electrode. The top edge electrode, the substrate disposed on the bottom electrode, and the bottom edge electrode are configured to generate a cleaning plasma to clean the bevel edge of the substrate. The bottom edge electrode and the bottom electrode are electrically coupled to one another through an RF circuit tunable to adjust the amount of RF current going between the substrate disposed on the bottom electrode, the bottom edge electrode and the top edge electrode.

Abstract translation: 这些实施例提供用于去除基板斜边缘上和附近的蚀刻副产物，电介质膜和金属膜的结构和机构，以及室内，以避免聚合物副产物和沉积膜的积聚并提高工艺产率。 在示例性实施例中，提供了构造成清洁基板的斜边缘的等离子体处理室。 等离子体处理室包括被配置为接收衬底的底部电极，其中底部电极耦合到射频（RF）电源。 等离子体处理室还包括围绕与底部电极相对的绝缘板的顶部边缘电极。 顶边电极电接地。 等离子体处理室还包括围绕底部电极的底部边缘电极。 底边电极与顶边缘电极相对。 上边缘电极，设置在底部电极上的基板和底部边缘电极被配置为产生清洁等离子体以清洁基板的斜边缘。 底边电极和底电极通过可调谐的RF电路彼此电耦合，以调节在设置在底部电极，底部边缘电极和顶部边缘电极之间的衬底之间的RF电流的量。

公开(公告)号：US20090084169A1

公开(公告)日：2009-04-02

申请号：US12233501

申请日：2008-09-18

Applicant: Andrew D. Bailey, III

Inventor： Andrew D. Bailey, III

IPC: G01B21/16

CPC classification number: H01L22/12 ,  G01B21/08 ,  G01B21/20 ,  G01B21/30 ,  H01L22/20

Abstract: An arrangement for quantifying a wafer bow. The arrangement is positioned within a plasma processing system is provided. The arrangement includes a support mechanism for holding a wafer. The arrangement also includes a first set of sensors, which is configured to collect a first set of measurement data for a plurality of data points on the wafer. The first set of measurement data indicates a minimum gap between the first set of sensors and the wafer. The first set of sensors is positioned in a first location, which is outside of a set of process modules of the plasma processing system.

Abstract translation: 用于量化晶片弓的布置。 该装置位于等离子体处理系统内。 该装置包括用于保持晶片的支撑机构。 该布置还包括第一组传感器，其被配置为收集晶片上的多个数据点的第一组测量数据。 第一组测量数据表示第一组传感器和晶片之间的最小间隙。 第一组传感器位于第一位置，其位于等离子体处理系统的一组处理模块之外。

公开(公告)号：US07486878B2

公开(公告)日：2009-02-03

申请号：US11612370

申请日：2006-12-18

Applicant: Jack Chen ,  Andrew D Bailey, III ,  Ben Mooring ,  Stephen J. Cain

Inventor： Jack Chen ,  Andrew D Bailey, III ,  Ben Mooring ,  Stephen J. Cain

IPC: G03B15/00 ,  G03B15/03 ,  G03B17/00 ,  G01R13/26

CPC classification number: H01L21/681 ,  H01L21/67259 ,  H01L21/67288

Abstract: A bevel inspection module for capturing images of a substrate is provided. The module includes a rotational motor, which is attached to a substrate chuck and is configured to rotate the substrate chuck thereby allowing the substrate to revolve. The module further includes a camera and an optic enclosure, which is attached to the camera and is configured to rotate, enabling light to be directed toward the substrate. The camera is mounted from a camera mount, which is configured to enable the camera to rotate on a 180 degree plane allowing the camera to capture images of at least one of a top view, a bottom view, and a side view of the substrate. The module yet also includes a backlight arrangement, which is configured to provide illumination to the substrate, thereby enabling the camera to capture the images, which shows contrast between the substrate and a background.

Abstract translation: 提供了一种用于捕获基板的图像的斜面检查模块。 模块包括旋转马达，其连接到基板卡盘并且构造成旋转基板卡盘，从而允许基板旋转。 该模块还包括照相机和光学外壳，其附接到相机并且被配置为旋转，使得光能够被引向基板。 照相机从照相机安装座安装，照相机安装件被配置为使照相机能够在180度平面上旋转，允许照相机拍摄基板的俯视图，底视图和侧视图中的至少一个的图像。 该模块还包括背光布置，其被配置为向基板提供照明，从而使得相机能够捕获显示基板和背景之间的对比度的图像。

公开(公告)号：US07480571B2

公开(公告)日：2009-01-20

申请号：US10966549

申请日：2004-10-15

Applicant: Arthur M. Howald ,  Andras Kuthi ,  Andrew D. Bailey, III

Inventor： Arthur M. Howald ,  Andras Kuthi ,  Andrew D. Bailey, III

IPC: C23F1001/00

CPC classification number: H01J37/32082 ,  H01J37/32183 ,  H01J37/3299 ,  H03H7/40 ,  H05H1/46

Abstract: Methods for improving the stability of RF power delivery to a plasma load are disclosed. The method includes adding an RF resistor and/or a power attenuator at one of many specific locations in the RF power system to lower the impedance derivatives while keeping the matching circuit substantially in tune with the RF transmission line.

Abstract translation: 公开了用于提高RF功率输送到等离子体负载的稳定性的方法。 该方法包括在RF功率系统中的许多特定位置之一处添加RF电阻器和/或功率衰减器，以降低阻抗导数，同时保持匹配电路与RF传输线基本一致。

公开(公告)号：US07413673B2

公开(公告)日：2008-08-19

申请号：US11109921

申请日：2005-04-19

Applicant: Shrikant P. Lohokare ,  Andras Kuthi ,  Andrew D. Bailey, III

Inventor： Shrikant P. Lohokare ,  Andras Kuthi ,  Andrew D. Bailey, III

IPC: H03J3/12

CPC classification number: H01J37/321 ,  H01J37/32174 ,  H01J37/32431 ,  H01J37/32623

Abstract: An apparatus and method for adjusting the voltage applied to a Faraday shield of an inductively coupled plasma etching apparatus is provided. An appropriate voltage is easily and variably applied to a Faraday shield such that sputtering of a plasma can be controlled to prevent and mitigate deposition of non-volatile reaction products that adversely affect an etching process. The appropriate voltage for a particular etching process or step is applied to the Faraday shield by simply adjusting a tuning capacitor. It is not necessary to mechanically reconfigure the etching apparatus to adjust the Faraday shield voltage.

Abstract translation: 提供了一种用于调整施加到电感耦合等离子体蚀刻装置的法拉第屏蔽的电压的装置和方法。 适当的电压容易且可变地施加到法拉第屏蔽，使得可以控制等离子体的溅射以防止和减轻不利地影响蚀刻工艺的非挥发性反应产物的沉积。 通过简单地调整调谐电容器，将特定蚀刻工艺或步骤的适当电压施加到法拉第屏蔽。 不需要机械地重新配置蚀刻装置来调节法拉第屏蔽电压。

公开(公告)号：US07347915B1

公开(公告)日：2008-03-25

申请号：US11326934

申请日：2006-01-05

Applicant: Douglas L. Keil ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Mark H. Wilcoxson ,  Andrew D. Bailey, III

Inventor： Douglas L. Keil ,  Wan-Lin Chen ,  Eric A. Hudson ,  S. M. Reza Sadjadi ,  Mark H. Wilcoxson ,  Andrew D. Bailey, III

IPC: H01L21/00

CPC classification number: H01L21/0273

Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

Abstract translation: 提供了通过在晶片上蚀刻层来制造半导体器件的方法。 在晶片上设置光致抗蚀剂层。 对光致抗蚀剂层进行图案化。 将晶片放置在处理室中。 通过在处理室中提供含有高能电子的硬化等离子体使光致抗蚀剂硬化，使光致抗蚀剂层硬化，其中高能电子具有密度。 该层在处理室内用蚀刻等离子体蚀刻，其中蚀刻等离子体中高能电子的密度小于硬化等离子体中高能电子的密度。

公开(公告)号：US07242185B1

公开(公告)日：2007-07-10

申请号：US11096012

申请日：2005-03-30

Applicant: Andrew D. Bailey, III

Inventor： Andrew D. Bailey, III

IPC: G01B7/06 ,  G01R33/12

CPC classification number: G01B7/105 ,  G01N27/9033

Abstract: A method of determining a thickness at a thickness position of a conductive film on a substrate with a center zone and an edge zone is disclosed. The method includes providing a set of thickness correlation curves at a set of sensor position radii from a center of the substrate to a position where a sensitivity of an eddy current sensor to the edge zone is greater than zero. The method also includes measuring a set of eddy current responses at a sensor position of the set of sensor position radii. The method further includes correlating the set of eddy current responses to the thickness at the thickness position.

Abstract translation: 公开了一种确定具有中心区域和边缘区域的基板上的导电膜的厚度位置处的厚度的方法。 该方法包括在从基板中心的一组传感器位置半径到涡流传感器对边缘区域的灵敏度大于零的位置处提供一组厚度相关曲线。 该方法还包括在传感器位置半径集合的传感器位置处测量一组涡流响应。 该方法还包括将该组涡流响应与厚度位置处的厚度相关联。

公开(公告)号：US07239737B2

公开(公告)日：2007-07-03

申请号：US10331194

申请日：2002-12-24

Applicant: Jorge Luque ,  Andrew D. Bailey, III ,  Mark Wilcoxson

Inventor： Jorge Luque ,  Andrew D. Bailey, III ,  Mark Wilcoxson

IPC: G06K9/00 ,  G11B27/00

CPC classification number: H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A graphical user interface for controlling analysis of a wafer map is provided. The user interface provides a graphical selection control for selecting a region of the wafer map for statistical analysis. The user interface is configured to generate statistical data for the selected region to complete the statistical analysis. The statistical data is then displayed for the selected region. Re-generation of the statistical data for display is performed upon detecting a change in the selected region.

Abstract translation: 提供了一种用于控制晶片映射分析的图形用户界面。 用户界面提供用于选择晶片图的区域以进​​行统计分析的图形选择控制。 用户界面被配置为生成所选区域的统计数据，以完成统计分析。 然后显示所选区域的统计数据。 在检测到所选择的区域的变化时，再次产生用于显示的统计数据。

公开(公告)号：US07232766B2

公开(公告)日：2007-06-19

申请号：US10769408

申请日：2004-01-30

Applicant: Andrew D. Bailey, III ,  Shrikant P. Lohokare

Inventor： Andrew D. Bailey, III ,  Shrikant P. Lohokare

IPC: H01L21/302

CPC classification number: H01L21/32115 ,  C23G5/00 ,  H01J37/32522 ,  H01J2237/022 ,  H01L21/32136 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/76838 ,  H01L21/7684

Abstract: A system and method of passivating an exposed conductive material includes placing a substrate in a process chamber and injecting a hydrogen species into the process chamber. A hydrogen species plasma is formed in the process chamber. A surface layer species is reduced from a top surface of the substrate is reduced. The reduced surface layer species are purged from the process chamber.

Abstract translation: 钝化暴露的导电材料的系统和方法包括将衬底放置在处理室中并将氢物质注入到处理室中。 在处理室中形成氢物质等离子体。 从基板的顶面减少的表面层物质减少。 还原的表面层物质从处理室中清除。