公开(公告)号：US06465315B1

公开(公告)日：2002-10-15

申请号：US09476527

申请日：2000-01-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/1045 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586

Abstract: A method of fabricating an integrated circuit with a source side compensation implant utilizes tilt-angle implants. An asymmetric channel profile is formed in which less dopants are located on a source side. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS).

Abstract translation: 使用源极侧补偿注入制造集成电路的方法利用倾斜角植入。 形成非对称沟道轮廓，其中较少的掺杂剂位于源侧。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。

公开(公告)号：US06455903B1

公开(公告)日：2002-09-24

申请号：US09491267

申请日：2000-01-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649

Abstract: An integrated circuit and method of fabricating integrated circuits is provided for an integrated circuit having threshold voltage adjustment. Unlike conventional methods and devices, threshold voltage adjustment is provided by an inert ion implantation process whereby inert ions are implanted into an underlying substrate. The implantation forms a semi-insulative layer comprised of an accumulation of inert ions. The inert ion region is formed between source and drain regions of a device on the integrated circuit. During operation of the device, the accumulation region confines the depth of the depletion layer. By confining the depth of the depletion layer, the threshold voltage of the device is reduced.

Abstract translation: 为具有阈值电压调整的集成电路提供集成电路和制造集成电路的方法。 与常规方法和装置不同，通过惰性离子注入工艺提供阈值电压调节，由此将惰性离子注入到下面的衬底中。 注入形成由惰性离子的积聚组成的半绝缘层。 惰性离子区域形成在集成电路上的器件的源极和漏极区域之间。 在装置运行期间，积聚区域限制耗尽层的深度。 通过限制耗尽层的深度，器件的阈值电压降低。

公开(公告)号：US06451644B1

公开(公告)日：2002-09-17

申请号：US09187618

申请日：1998-11-06

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L218234

CPC classification number: H01L21/2807 ,  H01L21/268 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4916

Abstract: An ultra-large scale integrated (ULSI) circuit includes MOSFETs which have a gate conductor with dopants distributed in a box-like distribution. The dopants also achieve high electrical activation. The MOSFETs utilize gate structures with heavily doped polysilicon material or heavily doped polysilicon and germanium material. The polysilicon and polysilicon and germanium materials are manufactured by utilizing amorphous semiconductor layers. Excimer laser annealing is utilized to activate the dopants and to provide a box-like dopant profile.

Abstract translation: 超大规模集成（ULSI）电路包括具有分布在盒状分布中的掺杂剂的栅极导体的MOSFET。 掺杂剂也可实现高电活化。 MOSFET利用具有重掺杂多晶硅材料或重掺杂多晶硅和锗材料的栅极结构。 通过利用非晶半导体层制造多晶硅和多晶硅和锗材料。 使用准分子激光退火来激活掺杂剂并提供盒状掺杂物分布。

公开(公告)号：US06448613B1

公开(公告)日：2002-09-10

申请号：US09846958

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L27148

CPC classification number: H01L21/28052 ,  H01L21/26586 ,  H01L21/28105 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659 ,  Y10S977/707

Abstract: A field effect transistor is fabricated to have a drain overlap and a source overlap to minimize series resistance between the gate and the drain and between the gate and the source of the field effect transistor. The parasitic Miller capacitance formed by the drain overlap and the source overlap is reduced by forming a depletion region at the sidewalls of the gate structure of the field effect transistor. The depletion region at the sidewalls of the gate structure is formed by counter-doping the sidewalls of the gate structure. The sidewalls of the gate structure at the drain side and the source side of the field effect transistor are doped with a type of dopant that is opposite to the type of dopant within the gate structure. Such dopant at the sidewalls of the gate structure forms a respective depletion region from the sidewall into approximately the edge of the drain overlap and source overlap that extends under the gate structure to reduce the parasitic Miller capacitance formed by the drain overlap and the source overlap.

Abstract translation: 制造场效应晶体管以具有漏极重叠和源重叠，以使栅极和漏极之间以及场效应晶体管的栅极和源极之间的串联电阻最小化。 通过在场效应晶体管的栅极结构的侧壁处形成耗尽区，减少由漏极重叠和源极重叠形成的寄生米勒电容。 通过对栅极结构的侧壁进行反掺杂来形成栅极结构的侧壁处的耗尽区。 在场效应晶体管的漏极侧和源极侧的栅极结构的侧壁掺杂有与栅极结构内的掺杂剂类型相反的掺杂剂。 在栅极结构的侧壁处的这种掺杂剂从侧壁形成相应的耗尽区，从而在栅极结构下延伸的漏极重叠和源极重叠的大致边缘，以减小由漏极重叠和源极重叠形成的寄生米勒电容。

公开(公告)号：US06445042B1

公开(公告)日：2002-09-03

申请号：US09687992

申请日：2000-10-13

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L2976

CPC classification number: H01L29/6659 ,  G01N21/9501 ,  G01R31/307 ,  G01R31/311 ,  H01J37/21 ,  H01J2237/2817 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  Y10S257/90 ,  Y10S977/869 ,  Y10S977/881 ,  Y10S977/901 ,  Y10S977/954

Abstract: An improved semiconductor device, such as a MOSFET with raised source/drain extensions on a substrate with isolation trenches etched into the surface of the substrate . The device has thin first dielectric spacers on the side of a gate and gate oxide and extend from the top of the gate to the surface of the substrate. Raised source/drain extensions are placed on the surface of a substrate, which extend from the first dielectric spacers to the isolation trenches. Thicker second dielectric spacers are placed adjacent to the first dielectric spacers and extend from the top of the first dielectric spacers to the raised source/drain extensions. Raised source/drain regions are placed on the raised source/drain extensions, and extend from the isolation trenches to the second dielectric spacers. The semiconductor device has very shallow source drain extensions which result in a reduced short channel effect.

Abstract translation: 改进的半导体器件，例如在衬底上具有升高的源极/漏极延伸的MOSFET，其具有蚀刻到衬底的表面中的隔离沟槽。 该器件在栅极和栅极氧化物一侧具有薄的第一介电间隔物，并从栅极的顶部延伸到衬底的表面。 引出的源极/漏极延伸部被放置在从第一电介质间隔物延伸到隔离沟槽的衬底的表面上。 更厚的第二电介质间隔物被放置成与第一电介质间隔物相邻并且从第一介电间隔物的顶部延伸到升高的源极/漏极延伸部分。 升高的源极/漏极区域放置在凸起的源极/漏极延伸部上，并且从隔离沟槽延伸到第二电介质间隔物。 半导体器件具有非常浅的源极漏极延伸，导致短沟道效应降低。

公开(公告)号：US06399450B1

公开(公告)日：2002-06-04

申请号：US09609613

申请日：2000-07-05

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66628 ,  H01L21/28525 ,  H01L29/7834

Abstract: A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source and an elevated drain region. The method includes providing an amorphous semiconductor material, doping the amorphous material at a source location and drain location and crystallizing the amorphous semiconductor material via solid phase epitaxy. The semiconductor material can be silicided. A shallow source drain implant can also be provided.

Abstract translation: 制造集成电路的方法利用固相外延形成升高的源极和升高的漏极区域。 该方法包括提供非晶半导体材料，在源极位置和漏极位置掺杂非晶态材料，并通过固相外延结晶非晶半导体材料。 半导体材料可以被硅化。 还可以提供浅源极漏极植入物。

公开(公告)号：US06395609B1

公开(公告)日：2002-05-28

申请号：US09812095

申请日：2001-03-19

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21331

CPC classification number: H01L29/7311

Abstract: A MOSBJT (Metal Oxide Semiconductor Bipolar Junction Transistor) is formed to have both the higher current drive capability of the BJT and the smaller device area of the scaled down MOSFET. The MOSBJT includes a collector region and an emitter region comprised of a semiconductor material with a first type of dopant. A base region is disposed between the collector region and the emitter region, and the base region is comprised of a semiconductor material with a second type of dopant that is opposite of the first type of dopant. Unlike a conventional BJT, a base terminal of the MOSBJT is comprised of a dielectric structure disposed over the base region and comprised of a gate structure disposed over the dielectric structure. Unlike a conventional MOSFET, the dielectric structure of the MOSBJT is relatively thin such that a tunneling current through the dielectric structure results when a turn-on voltage is applied on the gate structure. This tunneling current is a base current of the MOSBJT. Furthermore, unlike a conventional MOSFET, the dielectric structure and the gate structure of the MOSBJT are not disposed over the collector region and the emitter region to prevent tunneling current between the gate structure and the collector and emitter regions.

Abstract translation: 形成MOSBJT（金属氧化物半导体双极结晶体管）以具有BJT的较高电流驱动能力和缩小的MOSFET的较小器件面积。 MOSBJT包括集电极区域和由具有第一类型掺杂剂的半导体材料组成的发射极区域。 基极区域设置在集电极区域和发射极区域之间，并且基极区域由具有与第一类型掺杂剂相反的第二类型掺杂剂的半导体材料构成。 与常规BJT不同，MOSBJT的基极端子由设置在基极区域上的电介质结构构成，并且包括设置在电介质结构上的栅极结构。 与常规MOSFET不同，MOSBJT的电介质结构相对较薄，使得当在栅极结构上施加导通电压时，导致通过电介质结构的隧穿电流。 该隧穿电流是MOSBJT的基极电流。 此外，与常规MOSFET不同，MOSBJT的电介质结构和栅极结构不会设置在集电极区域和发射极区域上，以防止栅极结构与集电极和发射极区域之间的隧穿电流。

公开(公告)号：US06391782B1

公开(公告)日：2002-05-21

申请号：US09597598

申请日：2000-06-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21311

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/3088 ,  H01L29/42384 ,  H01L29/66795

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure above active lines manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process. The gate structure can surround more than one side of the active line.

Abstract translation: 超大规模集成（ULSI）电路包括MOSFET。 MOSFET可以包括通过利用间隔结构作为掩模制造的有源线上的栅极结构。 间隔结构可以是在回蚀工艺中形成的二氧化硅。 栅极结构可以围绕有源线的多于一侧。

公开(公告)号：US06391753B1

公开(公告)日：2002-05-21

申请号：US09597624

申请日：2000-06-20

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L214763

CPC classification number: H01L21/0337 ,  H01L21/2815 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/823437 ,  H01L21/823828 ,  H01L21/84

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs. The MOSFETs can include a gate structure manufactured by utilizing a spacer structure as a mask. The spacer structure can be silicon dioxide formed in an etch back process.

Abstract translation: 超大规模集成（ULSI）电路包括MOSFET。 MOSFET可以包括通过利用间隔结构作为掩模制造的栅极结构。 间隔结构可以是在回蚀工艺中形成的二氧化硅。

公开(公告)号：US06376320B1

公开(公告)日：2002-04-23

申请号：US09712995

申请日：2000-11-15

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L29/66545

Abstract: For fabricating a field effect transistor having a gate structure on a gate dielectric within an active device area of a semiconductor substrate, a hardmask dielectric material covers a top surface of the gate structure. A drain silicide is formed with a drain contact junction that is exposed, and a source silicide is formed with a source contact junction that is exposed. The drain silicide and the source silicide have a first thickness and are comprised of a first silicide material. The hardmask dielectric material that covers the top surface of the gate structure prevents formation of silicide with the gate structure during formation of the drain silicide and the source silicide. An encapsulating dielectric material is then deposited to cover the drain silicide and the source silicide using a low temperature of less than about 400° Celsius. The hardmask dielectric material is etched away from the top surface of the gate structure to expose the top surface of the gate structure. A gate silicide is formed with the gate structure, and the gate silicide has a second thickness and is comprised of a second silicide material. The encapsulating dielectric material covering the drain silicide and the source silicide prevents further formation of the drain silicide and the source silicide during formation of the gate silicide. The present invention may be used to particular advantage when the first thickness of the drain and source suicides is less than the second thickness of the gate silicide and when the first silicide material of the drain and source silicides is different from the second silicide material of the gate silicide.

Abstract translation: 为了制造在半导体衬底的有源器件区域内的栅极电介质上具有栅极结构的场效应晶体管，硬掩模电介质材料覆盖栅极结构的顶表面。 漏极硅化物形成有露出的漏极接触结，并且源极硅化物形成有暴露的源极接触结。 漏极硅化物和源硅化物具有第一厚度并且由第一硅化物材料构成。 覆盖栅极结构的顶表面的硬掩模电介质材料防止了在形成漏极硅化物和源极硅化物期间与栅极结构形成硅化物。 然后使用低于约400℃的低温沉积封装介电材料以覆盖漏极硅化物和源硅化物。 将硬掩模介电材料从栅极结构的顶表面蚀刻掉以露出栅极结构的顶表面。 栅极硅化物与栅极结构形成，并且栅极硅化物具有第二厚度并且由第二硅化物材料构成。 覆盖漏极硅化物和源硅化物的封装电介质材料防止在形成栅极硅化物期间进一步形成漏极硅化物和源极硅化物。 当漏极和源自身的第一厚度小于栅极硅化物的第二厚度时，并且当漏极和源极硅化物的第一硅化物材料不同于第二硅化物材料时，本发明可以被用于特别有利的 栅极硅化物。