公开(公告)号：US06259140B1

公开(公告)日：2001-07-10

申请号：US09410360

申请日：1999-09-30

Applicant: Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

Inventor： Meng-Hwang Liu ,  Cheng-Shang Lai ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A semiconductor device is formed on a substrate having an ESD region and an internal region. A protective layer is formed over a portion of the ESD region to be protected from formation of silicide and suicide is formed on portions of the Internal and ESD region which remain unprotected by the protective layer. A portion of the protective layer is removed to form the remaining portions of the protective layer into sidewall spacers adjacent to a gate electrode included in the ESD region.

Abstract translation: 半导体器件形成在具有ESD区域和内部区域的衬底上。 在ESD区域的一部分上形成保护层以防止硅化物的形成，并且在保护层未保护的内部和ESD区域的部分上形成硅化物。 保护层的一部分被去除，以将保护层的剩余部分形成为与包括在ESD区域中的栅电极相邻的侧壁间隔。

公开(公告)号：US06194829B1

公开(公告)日：2001-02-27

申请号：US09575247

申请日：2000-05-22

Applicant: Nai-Cheng Lu

Inventor： Nai-Cheng Lu

IPC: H01J1304

CPC classification number: H01L29/7881 ,  G11C16/0416 ,  H01J9/025 ,  H01J19/24 ,  H01J21/105

Abstract: A micro vacuum tube includes a disk (7) having an axis and formed of successive planar layers of a first conductive layer (2), a first dielectric layer (3), a second conductive layer (4), and a second dielectric layer(5), a hole along the axis of the cylinder extends through the first dielectric layer (3), the second conductive layer (4), and the second dielectric layer (5), a cusp shaped microtip (62) centrally located over, and extending into, the hole is separated from and supported by, a pole (75) that rests on the second dielectric layer, and a cap (82) seals the microtip, the pole (75) and the hole in a permanent vacuum environment.

Abstract translation: 微型真空管包括具有轴线并由第一导电层（2），第一介电层（3），第二导电层（4）和第二电介质层（3）的连续平面层形成的盘（7） 沿着圆柱体的轴线延伸穿过第一介电层（3），第二导电层（4）和第二介电层（5），位于中心的尖尖形微尖头（62），以及 所述孔与所述第二电介质层上的极（75）分离并由其支撑，并且帽（82）在永久真空环境中密封所述微尖端，所述极（75）和所述孔。

公开(公告)号：US06175519B1

公开(公告)日：2001-01-16

申请号：US09359197

申请日：1999-07-22

Applicant: Tao Cheng Lu ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

Inventor： Tao Cheng Lu ,  Mam Tsung Wang ,  Chin Hsi Lin ,  Ful Long Ni

IPC: G11C1606

CPC classification number: G11C16/0491 ,  G11C5/063

Abstract: In a virtual ground semiconductor memory device such as an EPROM or a Flash EPROM, a program disturb inhibited unit is operatively connected to a memory array. The memory array includes a plurality of metal virtual ground and bit lines, with at least two bit line selection transistors connected to each of the metal lines. The program disturb inhibited is connected to each virtual ground line and each bit line. In this structure, one metal pitch is connected to two buried diffusion lines. The program inhibited unit includes a plurality of program disturb inhibited transistors, wherein each transistor is connected between a virtual ground and a bit line. A DWL and a DWR dummy line are connected to control the plurality of program disturb inhibited transistors. By combining the program disturb inhibit unit with the memory array, a conventional array structure which has only been suitable for MROM applications can be applied to an EPROM or a Flash EEPROM, allowing the cell size to be reduced.

Abstract translation: 在诸如EPROM或闪存EPROM的虚拟地面半导体存储器件中，程序干扰抑制单元可操作地连接到存储器阵列。 存储器阵列包括多个金属虚拟接地和位线，其中至少两个位线选择晶体管连接到每个金属线。 禁止的程序干扰连接到每个虚拟接地线和每个位线。 在这种结构中，一个金属间距连接到两个掩埋的扩散线。 程序禁止单元包括多个编程干扰禁止晶体管，其中每个晶体管连接在虚拟地和位线之间。 连接DWL和DWR虚拟线以控制多个编程干扰被禁止的晶体管。 通过将编程干扰抑制单元与存储器阵列组合，仅适用于MROM应用的常规阵列结构可以应用于EPROM或闪速EEPROM，从而可以减小单元大小。

公开(公告)号：US6083069A

公开(公告)日：2000-07-04

申请号：US108414

申请日：1998-07-01

Applicant: Nai-Cheng Lu

Inventor： Nai-Cheng Lu

IPC: G11C16/04 ,  H01J9/02 ,  H01J19/24 ,  H01J21/10 ,  H01L29/788

CPC classification number: H01L29/7881 ,  G11C16/0416 ,  H01J19/24 ,  H01J21/105 ,  H01J9/025

Abstract: A micro vacuum tube is described. The process for manufacturing it begins with the deposition of two layers of polysilicon or metal, separated by dielectric layers, topping them with a layer of silicon nitride, and forming these into the shape of a disk. A hole is etched in the silicon nitride and then lined with a spacer, causing the width of the hole to decrease from top to bottom. When the hole is partially filled with a sacrificial layer the latter has a depression at its center which may be used as a mold for a microtip. To allow for easy removal of the sacrificial layer, pole holes are etched in it. These become support poles after the microtip material has been deposited over the sacrificial layer (which gets removed in its entirety). As an alternative to a microtip, a micro razor edge may be used for the cold emitter. A cap deposited over the structure while it is in vacuo serves to keep it under permanent vacuum.

Abstract translation: 描述微型真空管。 其制造方法开始于沉积两层多晶硅或金属，由电介质层分开，用氮化硅层顶起来，并将其形成为盘形。 在氮化硅中蚀刻孔，然后用间隔物衬里，导致孔的宽度从顶部到底部减小。 当孔部分地填充有牺牲层时，其在其中心处具有凹陷，其可以用作微尖端的模具。 为了容易地去除牺牲层，在其中蚀刻极孔。 在微焊料材料已经沉积在牺牲层上（其被整体去除）之后，它们变成支撑极。 作为微尖端的替代，微型剃刀边缘可用于冷发射器。 在真空下沉积在结构上的盖子用于将其保持在永久真空下。

公开(公告)号：US6046482A

公开(公告)日：2000-04-04

申请号：US935072

申请日：1997-09-25

Applicant: Tao Cheng Lu ,  Mam-Tsung Wang

Inventor： Tao Cheng Lu ,  Mam-Tsung Wang

IPC: H01L21/8246 ,  H01L29/76

CPC classification number: H01L27/1124

Abstract: A mask read-only-memory cell structure without ROM code implantation is presented. By using double polysilicon technology, ROM code cells which store data "0" can be replaced by cells with double polysilicon layers and an insulating layer between them. Normal cells with double polysilicon layers but without an insulating layer between them form normal cells store data "1". According to the invention, further scaling of mask ROM is possible and operating condition can be released because of high junction breakdown voltage. Furthermore, the double polysilicon technology makes redundancy circuit more easily to implement.

Abstract translation: 提出了一种没有ROM代码植入的掩模只读存储单元结构。 通过使用双重多晶硅技术，存储数据“0”的ROM代码单元可以由具有双多晶硅层的单元和它们之间的绝缘层代替。 具有双多晶硅层但在它们之间没有绝缘层的正电池形成正常电池存储数据“1”。 根据本发明，掩模ROM的进一步缩放是可能的，并且由于高的结击穿电压可以释放操作条件。 此外，双晶体技术使得冗余电路更容易实现。

公开(公告)号：US5963808A

公开(公告)日：1999-10-05

申请号：US783995

申请日：1997-01-15

Applicant: Wenpin Lu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

Inventor： Wenpin Lu ,  Tao-Cheng Lu ,  Mam-Tsung Wang

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/7883

Abstract: A memory cell having an asymmetric source and drain connection to buried bit-lines providing a Fowler-Nordheim tunneling region and a non-tunneling region defined by a bird's beak encroachment on each of the cells. A nonvolatile semiconductor memory device comprising row and column arrangement of the cells in which adjacent columns of cells share a single bit-line. The method for manufacturing a memory cell having asymmetric source and drain regions and comprising the steps of: (1) forming a dielectric covering a semiconductor substrate of a first conductivity type; (2) forming a column of floating gates on the dielectric; (3) forming an inhibit mask adjacent a first side of the column of floating gates; (4) implanting a dopant adjacent the first side and a second side of the column of floating gates, the first dopant having a second conductivity type opposite the first conductivity type; (5) forming a thermal oxide adjacent the first and second side of the column of floating gates such that the dopant adjacent the first side of the column is separated from the floating gates by the dielectric and the dopant adjacent the second side of the column is separated from the floating gates by a bird's beak encroachment of the thermal oxide formation; and (6) completing formation of control gate dielectric and control gates.

Abstract translation: 具有不对称的源极和漏极连接到具有Fowler-Nordheim隧道区域的掩埋位线的存储单元以及由每个单元上的鸟喙侵入限定的非隧穿区域。 一种非易失性半导体存储器件，包括单元的行和列排列，其中相邻列的单元共享单个位线。 一种制造具有不对称源区和漏区的存储单元的方法，包括以下步骤：（1）形成覆盖第一导电类型的半导体衬底的电介质; （2）在电介质上形成一列浮栅; （3）在所述浮栅的所述列的第一侧附近形成抑制掩模; （4）在所述浮栅的所述第一侧和所述第二侧附近注入掺杂剂，所述第一掺杂剂具有与所述第一导电类型相反的第二导电类型; （5）在浮置栅极列的第一和第二侧附近形成热氧化物，使得邻近该列的第一侧的掺杂剂通过电介质离开浮动栅极并且邻近该第二侧的掺杂剂是 通过鸟喙侵蚀热氧化物形成与浮动门分离; （6）完成控制栅介质和控制栅的形成。

公开(公告)号：US5818675A

公开(公告)日：1998-10-06

申请号：US744000

申请日：1996-11-04

Applicant: Chao-Cheng Lu

Inventor： Chao-Cheng Lu

IPC: H02M1/00 ,  H02M1/32 ,  H05B41/285 ,  H02H3/00

CPC classification number: H02M1/32 ,  H05B41/2851

Abstract: The protection device of an electronic circuit is an electronic AC circuit protection device. The protection device has the characteristic of over-voltage protection, over-current protection, electronic switch, and soft start. Devices of the protection circuit are electronic box, electronic devices box, and power factor regulator that is designed in the structure of L.C. in parallel on the source side of the protection circuit. The protection circuit can be applied in switching power supply, electronic ballast, etc., electronic circuit devices. The main electrical electronic devices include Triac Thyristor, Silicon Controlled Rectifier, Phototriac Coupler and Photothyistor Coupler etc. The protection device has characteristic of standing surge current that solving the problem of life and reliability of electronic devices in now a day. The invention is a necessary protection device for electrical industrial.

Abstract translation: 电子电路的保护装置是电子交流电路保护装置。 保护装置具有过电压保护，过流保护，电子开关和软启动等特点。 保护电路的设备是电子箱，电子设备箱和功率因数调节器，其设计在L.C.的结构中。 并联在保护电路的源极侧。 保护电路可应用于开关电源，电子镇流器等电子电路装置。 主要电子设备包括三端双向晶闸管，硅控整流器，光电耦合器和光电晶体耦合器等。保护器件具有稳定的浪涌电流特性，可以解决电子设备的使用寿命和可靠性问题。 本发明是电气工业的必要保护装置。

公开(公告)号：US5420494A

公开(公告)日：1995-05-30

申请号：US188820

申请日：1994-01-31

Applicant: Chao-Cheng Lu

Inventor： Chao-Cheng Lu

IPC: H02J7/02 ,  H02J7/04

CPC classification number: H02J7/022

Abstract: A battery charging device capable of charging any variety of rechargeable batteries and capable of being powered by either a 110 volt or a 220 volt A.C. power source. The battery charging device comprises an integrator circuit having a D.C. power source; a voltage comparator; a solid state relay; a D.C. output circuit; a positive voltage feedback circuit; and a negative voltage feedback circuit. The integrator circuit receives A.C. power from an A.C. power source and provides an output to the voltage comparator. The voltage comparator, in turn, is connected so as to provide an output to the solid state relay. The solid state relay preferably includes a zero voltage closing circuit and provides an output to the D.C. output circuit. The D.C. output circuit is connected to a battery-to-be-charged and provides an output D.C. voltage thereto. The D.C. output circuit is also connected to and provides outputs to the negative and positive feedback circuits which, in turn, provide feedback to the voltage comparator. Preferably, optical coupling devices connect the output from the voltage comparator to the solid state relay, as well as the positive and negative feedback circuits to the voltage comparator.

Abstract translation: 一种电池充电装置，能够对任意种类的可充电电池充电，并且能够由110伏或220伏交流电源供电。 电池充电装置包括具有直流电源的积分器电路; 电压比较器; 固态继电器; 直流输出电路; 正电压反馈电路; 和负电压反馈电路。 积分器电路从交流电源接收交流电源，并向电压比较器提供输出。 电压比较器依次连接，以向固态继电器提供输出。 固态继电器优选地包括零电压闭合电路并且向直流输出电路提供输出。 直流输出电路连接到要充电的电池，并向其提供输出直流电压。 直流输出电路还连接到负反馈电路和正反馈电路，输出电路反过来向电压比较器提供反馈。 优选地，光耦合装置将来自电压比较器的输出连接到固态继电器，以及将正和负反馈电路连接到电压比较器。

公开(公告)号：US5338991A

公开(公告)日：1994-08-16

申请号：US997695

申请日：1992-12-28

Applicant: Chao-Cheng Lu

Inventor： Chao-Cheng Lu

IPC: H02H11/00 ,  H03K17/70 ,  H03K17/78

CPC classification number: H02H11/002

Abstract: A solid state relay having an input circuit and a triac Darlington circuit coupled by a phototriac circuit. The input circuit having a bipolar indicator lamp for identifying the polarity and presence of an input voltage. The phototriac circuit and the triac Darlington circuit each having bipolar indicator lamps to indicate ON/OFF operation of respective triacs therein.

Abstract translation: 固态继电器，具有输入电路和由光驱三极管组合达林顿电路耦合。 输入电路具有用于识别极性和存在输入电压的双极性指示灯。 光电三极管电路和三端双向可控硅开关元件Darlington电路各自具有双极指示灯，用于指示其中各自的三端双向可控硅开关的ON / OFF操作。

公开(公告)号：US5329193A

公开(公告)日：1994-07-12

申请号：US974533

申请日：1992-11-12

Applicant: Chao-Cheng Lu

Inventor： Chao-Cheng Lu

IPC: H03K17/732 ,  H03K17/28 ,  H03K5/24

CPC classification number: H03K17/732

Abstract: A new computer controller is disclosed for controlling the output voltage of a SCR controller to a load. The computer controller includes a computer unit comprising a first pulse generator, a central processing unit, a first voltage comparator and a digital analog converter, and a control unit controlled by the computer unit and connected to the load through the SCR controller and consisting of a second pulse generator, an integrator circuit, a second voltage comparator, a turn-on circuit and a turn-off circuit.

Abstract translation: 公开了一种用于控制SCR控制器对负载的输出电压的新型计算机控制器。 计算机控制器包括计算机单元，其包括第一脉冲发生器，中央处理单元，第一电压比较器和数字模拟转换器，以及由计算机单元控制并通过SCR控制器连接到负载的控制单元， 第二脉冲发生器，积分器电路，第二电压比较器，导通电路和关断电路。