公开(公告)号：US08355282B2

公开(公告)日：2013-01-15

申请号：US12818095

申请日：2010-06-17

申请人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： G11C16/04

CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

摘要翻译： 非易失性存储器系统包括一个或多个非易失性存储器单元。 每个非易失性存储单元提供浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。 耦合装置位于第一导电区域中。 第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。 第二浮栅晶体管位于第三导电区域中。 这种非易失性存储单元进一步提供两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。 浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

公开(公告)号：US20130010518A1

公开(公告)日：2013-01-10

申请号：US13413626

申请日：2012-03-06

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C17/00 ,  H01L27/088

CPC分类号： H01L27/11206 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.

摘要翻译： 提供具有耦合通道的反熔丝存储器。 反熔丝存储器包括第一导电类型的衬底，第二导电类型的掺杂区域，耦合栅极，栅极介电层，反熔丝栅极和反熔丝层。 衬底具有隔离结构。 掺杂区域设置在衬底中。 在掺杂区域和隔离结构之间限定沟道区域。 耦合栅极设置在掺杂区域和隔离结构之间的衬底上。 耦合栅极与掺杂区域相邻。 栅极电介质层设置在耦合栅极和衬底之间。 反熔丝栅极设置在耦合栅极和隔离结构之间的衬底上。 反熔丝栅极和耦合栅极之间具有间隔。 反熔丝层设置在反熔丝栅极和衬底之间。

公开(公告)号：US20120276700A1

公开(公告)日：2012-11-01

申请号：US13549525

申请日：2012-07-16

申请人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Shih-Jye Shen

发明人： Ching-Hsiang Hsu ,  Ching-Sung Yang ,  Shih-Jye Shen

IPC分类号： H01L21/336

CPC分类号： H01L27/112 ,  G11C17/12 ,  H01L27/1126

摘要： A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor.

摘要翻译： 掩模定义的只读存储器阵列形成在衬底上，并且包括具有相反极性的第一ROM位和第二ROM位。 第一ROM位具有形成在衬底的第一区域上的第一MOS晶体管和第一阻挡层。 第一MOS晶体管的第二源极/漏极区域和第一扩散区域形成在第一块层的相对侧上的衬底的第一区域中。 第二ROM位包括第二MOS晶体管。

公开(公告)号：US20120236635A1

公开(公告)日：2012-09-20

申请号：US13485920

申请日：2012-06-01

申请人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： G11C16/04 ,  H01L29/788 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

摘要翻译： 非易失性存储器系统包括一个或多个非易失性存储器单元。 每个非易失性存储单元包括浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。 耦合装置位于第一导电区域中。 第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。 第二浮栅晶体管位于第三导电区域中。 这种非易失性存储单元还包括两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。 浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

公开(公告)号：US20120223381A1

公开(公告)日：2012-09-06

申请号：US13191424

申请日：2011-07-26

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： H01L21/336 ,  H01L29/792

CPC分类号： H01L29/792 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833

摘要： A non-volatile memory structure is disclosed. LDD regions may be optionally formed through an ion implantation using a mask for protection of a gate channel region of an active area. Two gates are apart from each other and disposed on an isolation structure on two sides of a middle region of the active area, respectively. The two gates may be each entirely disposed on the isolation structure or partially to overlap a side portion of the middle region of the active area. A charge-trapping layer and a dielectric layer are formed between the two gates and on the active area to serve for a storage node function. They may be further formed onto all sidewalls of the two gates to serve as spacers. Source/drain regions are formed through ion implantation using a mask for protection of the gates and the charge-trapping layer.

摘要翻译： 公开了一种非易失性存储器结构。 可以通过使用用于保护有源区的栅极沟道区的掩模的离子注入任选地形成LDD区。 两个门彼此分开并且分别设置在有源区域的中间区域的两侧上的隔离结构上。 两个门可以各自完全设置在隔离结构上，或者部分地与有效区域的中间区域的侧部重叠。 在两个门之间和有源区域上形成电荷俘获层和电介质层，用于存储节点功能。 它们可以进一步形成在两个门的所有侧壁上，用作间隔物。 通过使用用于保护栅极和电荷俘获层的掩模的离子注入形成源/漏区。

公开(公告)号：US20120163072A1

公开(公告)日：2012-06-28

申请号：US13414734

申请日：2012-03-08

申请人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Hsin-Ming Chen ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L21/28282 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory cell with dual functions includes a substrate, a first gate, a second gate, a third gate, a charge storage layer, a first diffusion region, a second diffusion region, and a third diffusion region. The second gate and the third gate are used for receiving a first voltage corresponding to a one-time programming function of the dual function and a second voltage corresponding to a multi-time programming function of the dual function. The first diffusion region is used for receiving a third voltage corresponding to the one-time programming function and a fourth voltage corresponding to the multi-time programming function. The second diffusion region is used for receiving a fifth voltage corresponding to the multi-time programming function.

摘要翻译： 具有双重功能的非易失性半导体存储单元包括基板，第一栅极，第二栅极，第三栅极，电荷存储层，第一扩散区域，第二扩散区域和第三扩散区域。 第二栅极和第三栅极用于接收对应于双功能的一次编程功能的第一电压和对应于双功能的多次编程功能的第二电压。 第一扩散区用于接收对应于一次编程功能的第三电压和对应于多次编程功能的第四电压。 第二扩散区用于接收对应于多次编程功能的第五电压。

公开(公告)号：US20090134452A1

公开(公告)日：2009-05-28

申请号：US12341984

申请日：2008-12-22

申请人： Ching-Sung Yang ,  Wei-Zhe Wong

发明人： Ching-Sung Yang ,  Wei-Zhe Wong

IPC分类号： H01L29/792

CPC分类号： H01L29/7887 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile memory includes a substrate, a memory unit array, (N+1) bit lines, M word lines, M first control gate lines, and M second control gate lines. The memory unit array includes N memory unit columns, and each memory unit column includes M memory units. The (N+1) bit lines are disposed on the substrate and arranged in parallel in the column direction, and the (N+1) bit lines are corresponding to the N memory unit columns. The M word lines are disposed on the substrate and arranged in parallel in the row direction. The M first control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the first memory cell in the same row. The M second control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the second memory cell in the same row.

摘要翻译： 非易失性存储器包括衬底，存储器单元阵列，（N + 1）位线，M字线，M个第一控制栅极线和M个第二控制栅极线。 存储单元阵列包括N个存储单元列，每个存储单元列包括M个存储单元。 （N + 1）位线设置在基板上，并且在列方向上并列布置，并且（N + 1）位线对应于N个存储单元列。 M字线设置在基板上并且在行方向上平行布置。 M个第一控制栅极线在行方向上平行布置在基板上，并且分别连接到同一行中的第一存储单元。 M个第二控制栅极线在行方向上平行布置在基板上，并分别连接到同一行中的第二存储单元。

公开(公告)号：US07491607B2

公开(公告)日：2009-02-17

申请号：US11750320

申请日：2007-05-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/3468 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

摘要翻译： 提供闪存单元。 将深井设置在基板中，并将井设置在深井内。 层叠栅极结构设置在基板上。 源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。 选择栅极设置在堆叠的栅极结构和源极区域之间。 第一栅极介电层设置在选择栅极和堆叠栅极结构之间。 第二栅极电介质层设置在选择栅极和衬底之间。 在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。 在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。 衬底上的导电插塞延伸穿过漏区和深掺杂区。

公开(公告)号：US20080316791A1

公开(公告)日：2008-12-25

申请号：US12191844

申请日：2008-08-14

申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： H01L27/112 ,  H01L27/11206

摘要： The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

摘要翻译： 本发明提供一种操作一次性可编程只读存储器（OTPROM）的方法。 OTPROM至少包括设置在基板上的选择晶体管，电极和电介质层，其中电极设置在选择晶体管的源极区域上，电介质层被设置在电极和源极区域之间。 操作一次性可编程只读存储器的方法包括执行编程操作以将数字数据值“1”写入存储器，并执行编程操作以将数字数据值“0”写入存储器。

公开(公告)号：US07336539B2

公开(公告)日：2008-02-26

申请号：US11750323

申请日：2007-05-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： G11C16/02 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/3468 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

摘要翻译： 提供闪存单元。 将深井设置在基板中，并将井设置在深井内。 层叠栅极结构设置在基板上。 源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。 选择栅极设置在堆叠的栅极结构和源极区域之间。 第一栅极介电层设置在选择栅极和堆叠栅极结构之间。 第二栅极电介质层设置在选择栅极和衬底之间。 在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。 在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。 衬底上的导电插塞延伸穿过漏区和深掺杂区。