公开(公告)号：US20080151645A1

公开(公告)日：2008-06-26

申请号：US12043146

申请日：2008-03-06

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： G11C16/06

CPC分类号： H01L29/7887 ,  H01L27/115 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/4232 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory including at least a substrate, a memory cell and source/drain regions is provided. The memory cell is disposed on the substrate and includes at least a first memory unit and a second memory unit. Wherein, the first memory unit, from the substrate up, includes a floating gate and a first control gate. The second memory unit is disposed on a sidewall of the first memory unit and includes a charge trapping layer and a second control gate. The two source/drain regions are disposed in the substrate at both sides of the memory cell.

摘要翻译： 提供至少包括衬底，存储单元和源极/漏极区域的非易失性存储器。 存储单元设置在基板上，并且至少包括第一存储单元和第二存储单元。 其中，第一存储单元从衬底向上包括浮动栅极和第一控制栅极。 第二存储器单元设置在第一存储器单元的侧壁上，并且包括电荷捕获层和第二控制栅极。 两个源极/漏极区域设置在存储单元两侧的衬底中。

公开(公告)号：US07235839B2

公开(公告)日：2007-06-26

申请号：US10904749

申请日：2004-11-25

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/3468 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

摘要翻译： 提供闪存单元。 将深井设置在基板中，并将井设置在深井内。 层叠栅极结构设置在基板上。 源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。 选择栅极设置在堆叠的栅极结构和源极区域之间。 第一栅极介电层设置在选择栅极和堆叠栅极结构之间。 第二栅极电介质层设置在选择栅极和衬底之间。 在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。 在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。 衬底上的导电插塞延伸穿过漏区和深掺杂区。

公开(公告)号：US06750504B2

公开(公告)日：2004-06-15

申请号：US10063444

申请日：2002-04-24

申请人： Ching-Sung Yang ,  Shih-Jye Shen ,  Wei-Zhe Wong ,  Ching-Hsiang Hsu

发明人： Ching-Sung Yang ,  Shih-Jye Shen ,  Wei-Zhe Wong ,  Ching-Hsiang Hsu

IPC分类号： H01L2972

CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L27/115

摘要： A low voltage single-poly flash memory cell includes a first ion well of a first conductivity type, a second ion well of a second conductivity type formed on the first ion well, a charge storage layer comprising a first insulating layer, a trapping layer, and a second insulating layer, located on the second ion well, a gate located on the charge storage layer, a sourceand a drain of the second conductivity type located in two sides of the charge storage layer, and an ion doped region of the first conductivity type formed in the second ion well and under and surrounding the source and at least a portion of a bottom of the first insulating layer.

摘要翻译： 低电压单聚光闪存单元包括第一导电类型的第一离子阱，形成在第一离子阱上的第二导电类型的第二离子阱，电荷存储层，其包含第一绝缘层，俘获层， 以及位于所述第二离子阱上的第二绝缘层，位于所述电荷存储层上的栅极，位于所述电荷存储层的两侧的所述第二导电类型的源极和漏极以及所述第一导电性的离子掺杂区域 形成在所述第二离子阱中并且在所述源的下面和周围以及所述第一绝缘层的底部的至少一部分。

公开(公告)号：US20090134452A1

公开(公告)日：2009-05-28

申请号：US12341984

申请日：2008-12-22

申请人： Ching-Sung Yang ,  Wei-Zhe Wong

发明人： Ching-Sung Yang ,  Wei-Zhe Wong

IPC分类号： H01L29/792

CPC分类号： H01L29/7887 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7923

摘要： A non-volatile memory includes a substrate, a memory unit array, (N+1) bit lines, M word lines, M first control gate lines, and M second control gate lines. The memory unit array includes N memory unit columns, and each memory unit column includes M memory units. The (N+1) bit lines are disposed on the substrate and arranged in parallel in the column direction, and the (N+1) bit lines are corresponding to the N memory unit columns. The M word lines are disposed on the substrate and arranged in parallel in the row direction. The M first control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the first memory cell in the same row. The M second control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the second memory cell in the same row.

摘要翻译： 非易失性存储器包括衬底，存储器单元阵列，（N + 1）位线，M字线，M个第一控制栅极线和M个第二控制栅极线。 存储单元阵列包括N个存储单元列，每个存储单元列包括M个存储单元。 （N + 1）位线设置在基板上，并且在列方向上并列布置，并且（N + 1）位线对应于N个存储单元列。 M字线设置在基板上并且在行方向上平行布置。 M个第一控制栅极线在行方向上平行布置在基板上，并且分别连接到同一行中的第一存储单元。 M个第二控制栅极线在行方向上平行布置在基板上，并分别连接到同一行中的第二存储单元。

公开(公告)号：US07491607B2

公开(公告)日：2009-02-17

申请号：US11750320

申请日：2007-05-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/3468 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

摘要翻译： 提供闪存单元。 将深井设置在基板中，并将井设置在深井内。 层叠栅极结构设置在基板上。 源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。 选择栅极设置在堆叠的栅极结构和源极区域之间。 第一栅极介电层设置在选择栅极和堆叠栅极结构之间。 第二栅极电介质层设置在选择栅极和衬底之间。 在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。 在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。 衬底上的导电插塞延伸穿过漏区和深掺杂区。

公开(公告)号：US20080316791A1

公开(公告)日：2008-12-25

申请号：US12191844

申请日：2008-08-14

申请人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

发明人： Ching-Sung Yang ,  Wei-Zhe Wong ,  Chih-Chen Cho

IPC分类号： G11C17/00 ,  G11C7/00

CPC分类号： H01L27/112 ,  H01L27/11206

摘要： The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory.

摘要翻译： 本发明提供一种操作一次性可编程只读存储器（OTPROM）的方法。 OTPROM至少包括设置在基板上的选择晶体管，电极和电介质层，其中电极设置在选择晶体管的源极区域上，电介质层被设置在电极和源极区域之间。 操作一次性可编程只读存储器的方法包括执行编程操作以将数字数据值“1”写入存储器，并执行编程操作以将数字数据值“0”写入存储器。

公开(公告)号：US07336539B2

公开(公告)日：2008-02-26

申请号：US11750323

申请日：2007-05-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang

发明人： Wei-Zhe Wong ,  Ching-Sung Yang

IPC分类号： G11C16/02 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C16/3468 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

摘要： A flash memory cell is provided. A deep well is disposed in a substrate and a well is disposed within the deep well. A stacked gate structure is disposed on the substrate. A source region and a drain region are disposed in the substrate on each side of the stacked gate structure. A select gate is disposed between the stacked gate structure and the source region. A first gate dielectric layer is disposed between the select gate and the stacked gate structure. A second gate dielectric layer is disposed between the select gate and the substrate. A shallow doped region is disposed in the substrate under the stacked gate structure and the select gate. A deep doped region is disposed in the substrate on one side of the stacked gate structure. The conductive plug on the substrate extends through the drain region and the deep doped region.

摘要翻译： 提供闪存单元。 将深井设置在基板中，并将井设置在深井内。 层叠栅极结构设置在基板上。 源极区域和漏极区域设置在堆叠栅极结构的每一侧上的衬底中。 选择栅极设置在堆叠的栅极结构和源极区域之间。 第一栅极介电层设置在选择栅极和堆叠栅极结构之间。 第二栅极电介质层设置在选择栅极和衬底之间。 在堆叠栅极结构和选择栅极之下的衬底中设置浅掺杂区域。 在堆叠栅极结构的一侧上的衬底中设置深掺杂区域。 衬底上的导电插塞延伸穿过漏区和深掺杂区。

公开(公告)号：US20070259497A1

公开(公告)日：2007-11-08

申请号：US11778655

申请日：2007-07-17

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L21/336

CPC分类号： G11C16/0416 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

摘要： A non-volatile memory is provided. A substrate has at least two isolation structures therein to define an active area. A well is located in the substrate. A shallow doped region is located in the well. At least two stacked gate structures are located on the substrate. Pocket doped regions are located in the substrate at the peripheries of the stacked gate structures; each of the pocket doped regions extends under the stacked gate structure. Drain regions are located in the pocket doped regions at the peripheries of the stacked gate structures. An auxiliary gate layer is located on the substrate between the stacked gate structures. A gate dielectric layer is located between the auxiliary gate layer and the substrate and between the auxiliary gate layer and the stacked gate structure. Plugs are located on the substrate and extended to connect with the pocket doped region and the drain regions therein.

摘要翻译： 提供非易失性存储器。 衬底在其中具有至少两个隔离结构以限定有效区域。 一个井位于基板中。 浅掺杂区域位于井中。 至少两个堆叠的栅极结构位于衬底上。 袋状掺杂区域位于堆叠栅极结构的周边的衬底中; 每个口袋掺杂区域在堆叠的栅极结构之下延伸。 漏极区位于堆叠栅极结构的周边的口袋掺杂区域中。 辅助栅极层位于堆叠栅极结构之间的衬底上。 栅极电介质层位于辅助栅极层和衬底之间，并且位于辅助栅极层和堆叠栅极结构之间。 插头位于衬底上并延伸以与其中的口袋掺杂区域和漏极区域连接。

公开(公告)号：US07154142B2

公开(公告)日：2006-12-26

申请号：US11158412

申请日：2005-06-21

申请人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

发明人： Wei-Zhe Wong ,  Ching-Sung Yang ,  Chih-Chen Cho

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926 ,  Y10S438/954

摘要： A non-volatile memory device having a substrate, an n type well, a p type well, a control gate, a composite dielectric layer, a source region and a drain region is provided. A trench is formed in the substrate. The n type well is formed in the substrate. The p type well is formed in the substrate above the n type well. The junction of p type well and the n type well is higher than the bottom of the trench. The control gate which protruding the surface of substrate is formed on the sidewalls of the trench. The composite dielectric layer is formed between the control gate and the substrate. The composite dielectric layer includes a charge-trapping layer. The source region and the drain region are formed in the substrate of the bottom of the trench respectively next to the sides of the control gate.

摘要翻译： 提供了具有基板，n型阱，p型阱，控制栅极，复合电介质层，源极区域和漏极区域的非易失性存储器件。 在衬底中形成沟槽。 在衬底中形成n型阱。 p型阱形成在n型阱上方的衬底中。 p型阱和n型阱的结点高于沟槽的底部。 突出基板表面的控制栅极形成在沟槽的侧壁上。 复合介质层形成在控制栅极和衬底之间。 复合介电层包括电荷捕获层。 源极区域和漏极区域分别形成在沟槽底部的衬底中，分别在控制栅极的侧面旁边。

公开(公告)号：US20060231888A1

公开(公告)日：2006-10-19

申请号：US11162893

申请日：2005-09-27

申请人： Ching-Sung Yang ,  Wei-Zhe Wong

发明人： Ching-Sung Yang ,  Wei-Zhe Wong

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A programmable and erasable digital switch device is provided. An N-type memory transistor and a P-type memory transistor are formed over a substrate. The N-type memory transistor includes a first N-type doped region, a second N-type doped region, a first charge storage layer and a first control gate. The P-type memory transistor includes a first P-type doped region, a second P-type doped region, a second charge storage layer and a second control gate. A common bit line doped region is formed between the N-type memory transistor and the P type memory transistor and electrically connects the first N-type region to the second P-type doped region. A word line electrically connects the first control gate to the second control gate.

摘要翻译： 提供可编程和可擦除的数字开关装置。 在衬底上形成N型存储晶体管和P型存储晶体管。 N型存储晶体管包括第一N型掺杂区，第二N型掺杂区，第一电荷存储层和第一控制栅极。 P型存储晶体管包括第一P型掺杂区，第二P型掺杂区，第二电荷存储层和第二控制栅极。 在N型存储晶体管和P型存储晶体管之间形成公共位线掺杂区域，并将第一N型区域电连接到第二P型掺杂区域。 字线将第一控制栅极电连接到第二控制栅极。