公开(公告)号：US11836574B2

公开(公告)日：2023-12-05

申请号：US17234469

申请日：2021-04-19

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mohammad H. S. Amin ,  Trevor Michael Lanting ,  Colin Enderud

IPC: G06N10/00

CPC classification number: G06N10/00

Abstract: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.

公开(公告)号：US20230385668A1

公开(公告)日：2023-11-30

申请号：US18203880

申请日：2023-05-31

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Aidan P. Roy ,  Fabian A. Chudak ,  Zhengbing Bian ,  William G. Macready ,  Robert B. Israel ,  Kelly T. R. Boothby ,  Sheir Yarkoni ,  Yanbo Xue ,  Dmytro Korenkevych

IPC: G06N10/00

CPC classification number: G06N10/00

Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

公开(公告)号：US20230169378A1

公开(公告)日：2023-06-01

申请号：US17988250

申请日：2022-11-16

Applicant: D-WAVE SYSTEMS INC.

Inventor： James A. King ,  William W. Bernoudy ,  Kelly T. R. Boothby ,  Pau Farré Pérez

IPC: G06N10/00 ,  G06F17/18 ,  G06F18/21 ,  G06F18/23213

CPC classification number: G06N10/00 ,  G06F17/18 ,  G06F18/217 ,  G06F18/23213

Abstract: Systems and methods are described for operating a hybrid computing system using cluster contraction for converting large, dense input to reduced input that can be easily mapped into a quantum processor. The reduced input represents the global structure of the problem. Techniques involve partitioning the input variables into clusters and contracting each cluster. The input variables can be partitioned using an Unweighted Pair Group Method with Arithmetic Mean algorithm. The quantum processor returns samples based on the reduced input and the samples are expanded to correspond to the original input.

公开(公告)号：US11663512B2

公开(公告)日：2023-05-30

申请号：US17584600

申请日：2022-01-26

Applicant: D-WAVE SYSTEMS INC.

Inventor： Steven P. Reinhardt ,  Andrew D. King ,  Loren J. Swenson ,  Warren T. E. Wilkinson ,  Trevor Michael Lanting

IPC: G06N10/00 ,  G05B19/042

CPC classification number: G06N10/00 ,  G05B19/042 ,  G05B2219/25071

Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.

公开(公告)号：US20230143506A1

公开(公告)日：2023-05-11

申请号：US17399375

申请日：2021-08-11

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mark W. Johnson ,  Paul I. Bunyk ,  Andrew J. Berkley ,  Richard G. Harris ,  Kelly T. R. Boothby ,  Loren J. Swenson ,  Emile M. Hoskinson ,  Christopher B. Rich ,  Jan E. S. Johansson

IPC: H10N60/12 ,  G06N10/00 ,  H10N60/80

CPC classification number: H10N60/124 ,  G06N10/00 ,  H10N60/805

Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

公开(公告)号：US11647590B2

公开(公告)日：2023-05-09

申请号：US16896554

申请日：2020-06-09

Applicant: D-WAVE SYSTEMS INC.

Inventor： Jeffrey P. Burress ,  Richard D. Neufeld ,  Surjit Singh Dhesi

IPC: H05K3/06 ,  H01L39/24

CPC classification number: H05K3/067 ,  H01L39/24 ,  H05K3/064

Abstract: A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch.

公开(公告)号：US11617272B2

公开(公告)日：2023-03-28

申请号：US16465765

申请日：2017-12-07

Applicant: D-WAVE SYSTEMS INC.

Inventor： Richard D. Neufeld

IPC: H05K3/42 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46

Abstract: A multilayer circuit board structure includes superconducting connections to internal layers thereof, for example by inclusion of superconducting vias. Two or more panels can each comprise respective electrically insulative substrates, each have one or more through-holes, and also include a respective bimetal foil on at least a portion of a respective surface thereof, which is patterned to form traces. The bimetal foil includes a first metal that is non-superconductive in a first temperature range and a second metal that is superconductive in the first temperature range. The panels are plated to deposit a third metal on exposed traces of the second metal, the third metal superconductive in the first temperature range. Panels are join (e.g., laminated) to form at least a three-layer superconducting printed circuit board with an inner layer, two outer layers, and superconducting vias between the inner layer and at least one of the two outer layers.

公开(公告)号：US11514223B2

公开(公告)日：2022-11-29

申请号：US17068388

申请日：2020-10-12

Applicant: D-WAVE SYSTEMS INC.

Inventor： Reza Molavi ,  Mark H. Volkmann ,  Paul I. Bunyk

IPC: G06F30/398 ,  G06N10/00 ,  G06F30/392 ,  G06F115/12

Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.

公开(公告)号：US11409426B2

公开(公告)日：2022-08-09

申请号：US17182975

申请日：2021-02-23

Applicant: D-WAVE SYSTEMS INC.

Inventor： Murray C. Thom ,  Fiona L. Hanington ,  Alexander Condello ,  William W. Bernoudy ,  Melody C. Wong ,  Aidan P. Roy ,  Kelly T. R. Boothby ,  Edward D. Dahl

IPC: G06F3/048 ,  G06F3/04847 ,  G06N10/00 ,  G06T11/20 ,  G06F3/04817 ,  G06F16/901

Abstract: A user interface (UI), data structures and algorithms facilitate programming, analyzing, debugging, embedding, and/or modifying problems that are embedded or to be embedded on an analog processor (e.g., quantum processor), increasing computational efficiency and/or accuracy of problem solutions. The UI provides graph representations (e.g., source graph, target graph and correspondence therebetween) with nodes and edges which may map to hardware components (e.g., qubits, couplers) of the analog processor. Characteristics of solutions are advantageously represented spatially associated (e.g., overlaid or nested) with characteristics of a problem. Characteristics (e.g., bias state) may be represented by color, pattern, values, icons. Issues (e.g., broken chains) may be detected and alerts provided. Problem representations may be modified via the UI, and a computer system may autonomously generate new instances of the problem representation, update data structures, embed the new instance and cause the new instance to be executed by the analog processor.

公开(公告)号：US20220215282A1

公开(公告)日：2022-07-07

申请号：US17602097

申请日：2020-04-09

Applicant: D-WAVE SYSTEMS INC.

Inventor： Mohammad H. Amin

IPC: G06N10/40 ,  G06N10/20

Abstract: A technique for improving the performance of non-stoquastic quantum processors is provided. Clusters of qubits with correlated behavior are identified in a problem for processing by the quantum processor. Couplings between qubits in a common cluster are modified according to a transformation (for example, a gauge transformation) so that they evolve slower and thus their dynamics freeze out later (for example, by flipping anti-ferromagnetic couplings to ferromagnetic couplings). Couplings between qubits that do not belong to the common cluster may be flipped the other way (for example, from ferromagnetic couplings to anti-ferromagnetic couplings) to accelerate their dynamics. The quantum processor is evolved and the results are modified according to an inverse transformation.