Systems and methods for achieving orthogonal control of non-orthogonal qubit parameters

    公开(公告)号:US11836574B2

    公开(公告)日:2023-12-05

    申请号:US17234469

    申请日:2021-04-19

    CPC classification number: G06N10/00

    Abstract: Achieving orthogonal control of non-orthogonal qubit parameters of a logical qubit allows for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain. A hybrid qubit is formed by communicatively coupling a dedicated second qubit to a first qubit. By tuning a programmable parameter of the second qubit of a hybrid qubit, an effective programmable parameter of the hybrid qubit is adjusted without affecting another effective programmable parameter of the hybrid qubit thereby achieving orthogonal control of otherwise non-orthogonal qubit parameters. The length of the logical qubit may thus be increased by communicatively coupling a plurality of such hybrid qubits together.

    SYSTEMS AND METHODS FOR ANALOG PROCESSING OF PROBLEM GRAPHS HAVING ARBITRARY SIZE AND/OR CONNECTIVITY

    公开(公告)号:US20230385668A1

    公开(公告)日:2023-11-30

    申请号:US18203880

    申请日:2023-05-31

    CPC classification number: G06N10/00

    Abstract: Computational systems implement problem solving using hybrid digital/quantum computing approaches. A problem may be represented as a problem graph which is larger and/or has higher connectivity than a working and/or hardware graph of a quantum processor. A quantum processor may be used determine approximate solutions, which solutions are provided as initial states to one or more digital processors which may implement classical post-processing to generate improved solutions. Techniques for solving problems on extended, more-connected, and/or “virtual full yield” variations of the processor's actual working and/or hardware graphs are provided. A method of operation in a computational system comprising a quantum processor includes partitioning a problem graph into sub-problem graphs, and embedding a sub-problem graph onto the working graph of the quantum processor. The quantum processor and a non-quantum processor-based device generate partial samples. A controller causes a processing operation on the partial samples to generate complete samples.

    Quantum annealing debugging systems and methods

    公开(公告)号:US11663512B2

    公开(公告)日:2023-05-30

    申请号:US17584600

    申请日:2022-01-26

    CPC classification number: G06N10/00 G05B19/042 G05B2219/25071

    Abstract: Computational systems and methods employ characteristics of a quantum processor determined or sampled between a start and an end of an annealing evolution per an annealing schedule. The annealing evolution can be reinitialized, reversed or continued after determination. The annealing evolution can be interrupted. The annealing evolution can be ramped immediately prior to or as part of determining the characteristics. The annealing evolution can be paused or not paused immediately prior to ramping. A second representation of a problem can be generated based at least in part on the determined characteristics from an annealing evolution performed on a first representation of the problem. The determined characteristics can be autonomously compared to an expected behavior, and alerts optionally provided and/or the annealing evolution optionally terminated based on the comparison. Iterations of annealing evolutions may be performed until an exit condition occurs.

    Systems and methods for etching of metals

    公开(公告)号:US11647590B2

    公开(公告)日:2023-05-09

    申请号:US16896554

    申请日:2020-06-09

    CPC classification number: H05K3/067 H01L39/24 H05K3/064

    Abstract: A method of fabricating a multilayer superconducting printed circuit board comprises first, forming a bimetal foil to overlie a substrate, the bimetal foil comprising a first layer of a first metal, a layer of a second metal, and a second layer of the first metal, and then etching the second layer of the first metal. Forming a bimetal foil to overlie a substrate may include forming a bimetal foil comprising a first layer of a normal metal, a layer of a superconducting metal, and a second layer of the normal metal. Etching the second layer of the first metal may include preparing a patterned image in the second layer of the first metal for etching, processing the patterned image through a cleaner, rinsing the patterned image, and then, immersing the patterned image in a microetch.

    Superconducting printed circuit board related systems, methods, and apparatus

    公开(公告)号:US11617272B2

    公开(公告)日:2023-03-28

    申请号:US16465765

    申请日:2017-12-07

    Abstract: A multilayer circuit board structure includes superconducting connections to internal layers thereof, for example by inclusion of superconducting vias. Two or more panels can each comprise respective electrically insulative substrates, each have one or more through-holes, and also include a respective bimetal foil on at least a portion of a respective surface thereof, which is patterned to form traces. The bimetal foil includes a first metal that is non-superconductive in a first temperature range and a second metal that is superconductive in the first temperature range. The panels are plated to deposit a third metal on exposed traces of the second metal, the third metal superconductive in the first temperature range. Panels are join (e.g., laminated) to form at least a three-layer superconducting printed circuit board with an inner layer, two outer layers, and superconducting vias between the inner layer and at least one of the two outer layers.

    Systems and methods to extract qubit parameters

    公开(公告)号:US11514223B2

    公开(公告)日:2022-11-29

    申请号:US17068388

    申请日:2020-10-12

    Abstract: Systems and methods are described to accurately extract device parameters and optimize the design of macroscopic superconducting structures, for example qubits. This method presents the advantage of reusing existing plaquettes to simulate different processor topologies. The physical elements of a qubits are extracted via plurality of plaquettes. Each plaquette contains at least one physical element of the qubit design and has two ports on each side. Each plaquette is concatenated to at least one other plaquette via two ports. The values of inductance (L), capacitance (C) and mutual inductance (M) and quantum critical point of the qubit design can be computed. Changing the physical elements of the qubit design and iterating the method allows to effortlessly refine the qubit design.

    SYSTEMS AND METHODS FOR IMPROVING THE PERFORMANCE OF NON-STOQUASTIC QUANTUM DEVICES

    公开(公告)号:US20220215282A1

    公开(公告)日:2022-07-07

    申请号:US17602097

    申请日:2020-04-09

    Inventor: Mohammad H. Amin

    Abstract: A technique for improving the performance of non-stoquastic quantum processors is provided. Clusters of qubits with correlated behavior are identified in a problem for processing by the quantum processor. Couplings between qubits in a common cluster are modified according to a transformation (for example, a gauge transformation) so that they evolve slower and thus their dynamics freeze out later (for example, by flipping anti-ferromagnetic couplings to ferromagnetic couplings). Couplings between qubits that do not belong to the common cluster may be flipped the other way (for example, from ferromagnetic couplings to anti-ferromagnetic couplings) to accelerate their dynamics. The quantum processor is evolved and the results are modified according to an inverse transformation.

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