公开(公告)号：US20100148182A1

公开(公告)日：2010-06-17

申请号：US12429388

申请日：2009-04-24

Applicant: Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

Inventor： Hong-Kee CHIN ,  Sang-Gab KIM ,  Woong-Kwon KIM ,  Yong-Mo CHOI ,  Seung-Ha CHOI ,  Shin-Il CHOI ,  Ho-Jun LEE ,  Jung-Suk BANG ,  Yu-Gwang JEONG

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/12 ,  H01L27/1248 ,  H01L27/1288

Abstract: A thin film transistor (TFT) substrate is provided in which a sufficiently large contact area between conductive materials is provided in a contact portion and a method of fabricating the TFT substrate. The TFT substrate includes a gate interconnection line formed on an insulating substrate, a gate insulating layer covering the gate interconnection line, a semiconductor layer arranged on the gate insulating layer, a data interconnection line including a data line, a source electrode and a drain electrode formed on the semiconductor layer, a first passivation layer formed on the data interconnection line and exposing the drain electrode, a second passivation layer formed on the first passivation film and a pixel electrode electrically connected to the drain electrode. An outer sidewall of the second passivation layer is positioned inside an outer sidewall of the first passivation layer.

Abstract translation: 提供一种薄膜晶体管（TFT）基板，其中在接触部分中提供导电材料之间的足够大的接触面积以及制造TFT基板的方法。 TFT基板包括形成在绝缘基板上的栅极互连线，覆盖栅极互连线的栅极绝缘层，布置在栅极绝缘层上的半导体层，包括数据线，源极和漏极的数据互连线 形成在所述半导体层上，形成在所述数据互连线上并暴露所述漏电极的第一钝化层，形成在所述第一钝化膜上的第二钝化层和与所述漏电极电连接的像素电极。 第二钝化层的外侧壁位于第一钝化层的外侧壁的内侧。

公开(公告)号：US20100006844A1

公开(公告)日：2010-01-14

申请号：US12464452

申请日：2009-05-12

Applicant: Woong-Kwon KIM ,  Jun-Ho SONG ,  Joo-Han KIM ,  In-Woo KIM ,  Ho-Jun LEE

Inventor： Woong-Kwon KIM ,  Jun-Ho SONG ,  Joo-Han KIM ,  In-Woo KIM ,  Ho-Jun LEE

IPC: H01L33/00 ,  H01L21/336

CPC classification number: H01L27/1288 ,  H01L27/124

Abstract: A thin-film transistor (“TFT”) array and a method of fabricating the TFT array panel include: an insulating substrate; a gate line and a data line which are insulated from each other on the insulating substrate and are arranged in a lattice; common wiring extended parallel to the gate line on the insulating substrate; a gate insulating film disposed on the gate line and the common wiring; a semiconductor layer disposed on the gate insulating film; contact holes which penetrate through the gate insulating film and the semiconductor layer disposed on the common wiring; a plurality of common electrodes connected to the common wiring by the contact holes and arranged parallel to each other; and a plurality of pixel electrodes arranged parallel to the plurality of common electrodes.

Abstract translation: 薄膜晶体管（“TFT”）阵列和制造TFT阵列面板的方法包括：绝缘基片; 栅极线和数据线，其在绝缘基板上彼此绝缘并且布置成格子; 公共布线平行于绝缘基板上的栅极线延伸; 设置在栅极线和公共布线上的栅极绝缘膜; 设置在所述栅极绝缘膜上的半导体层; 穿过栅极绝缘膜的接触孔和布置在公共布线上的半导体层; 多个公共电极通过接触孔连接到公共布线并且彼此平行布置; 以及平行于所述多个公共电极排列的多个像素电极。

公开(公告)号：US20090068822A1

公开(公告)日：2009-03-12

申请号：US12177490

申请日：2008-07-22

Applicant: Yong-Jin KIM ,  Ji-Hoon KIM ,  Dong-Kun LEE ,  Doo-Soo KIM ,  Ho-Jun LEE

Inventor： Yong-Jin KIM ,  Ji-Hoon KIM ,  Dong-Kun LEE ,  Doo-Soo KIM ,  Ho-Jun LEE

IPC: H01L21/20 ,  C30B25/00

CPC classification number: C30B29/406 ,  C30B25/02 ,  C30B25/18

Abstract: Provided is a method for preparing a substrate for growing gallium nitride and a gallium nitride substrate. The method includes performing thermal cleaning on a surface of a silicon substrate, forming a silicon nitride (Si3N4) micro-mask on the surface of the silicon substrate in an in situ manner, and growing a gallium nitride layer through epitaxial lateral overgrowth (ELO) using an opening in the micro-mask. According to the method, by improving the typical ELO, it is possible to simplify the method for preparing the substrate for growing gallium nitride and the gallium nitride substrate and reduce process cost.

Abstract translation: 提供一种制备用于生长氮化镓和氮化镓衬底的衬底的方法。 该方法包括在硅衬底的表面上进行热清洗，以原位方式在硅衬底的表面上形成氮化硅（Si 3 N 4）微掩模，并通过外延横向过度生长（ELO）生长氮化镓层， 在微面罩中使用开口。 根据该方法，通过改善典型的ELO，可以简化制备用于生长氮化镓和氮化镓衬底的衬底的方法，并降低工艺成本。

公开(公告)号：US20080142846A1

公开(公告)日：2008-06-19

申请号：US12002338

申请日：2007-12-14

Applicant: Doo-Soo Kim ,  Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee

Inventor： Doo-Soo Kim ,  Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee

IPC: H01L29/267 ,  H01L21/205

CPC classification number: H01L21/02658 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/0254

Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.

Abstract translation: 氮化镓半导体衬底及其制造方法技术领域本发明涉及氮化镓衬底等氮化物半导体衬底及其制造方法。 本发明在基底基板的下表面上形成多个沟槽，该多个沟槽被配置为当从基底基板的中心部分向周边部分生长氮化物半导体膜时，吸收或减小施加更大的应力。 也就是说，本发明在基底基板的下表面上形成沟槽，使得间距变得较小，或者宽度或深度从基底基板的中心部朝向周边部分变大。

公开(公告)号：US20080105881A1

公开(公告)日：2008-05-08

申请号：US11982716

申请日：2007-11-02

Applicant: Yong-Jin Kim ,  Doo-Soo Kim ,  Ho-Jun Lee ,  Dong-Kun Lee

Inventor： Yong-Jin Kim ,  Doo-Soo Kim ,  Ho-Jun Lee ,  Dong-Kun Lee

IPC: H01L33/00 ,  H01L29/06 ,  H01L21/205

CPC classification number: H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L33/20 ,  H01L33/38

Abstract: The present invention relates to a compound semiconductor substrate and a method for manufacturing the same. The present invention provides the manufacturing method which coats spherical balls on a substrate, forms a metal layer between the spherical balls, removes the spherical balls to form openings, and grows a compound semiconductor layer from the openings. According to the present invention, the manufacturing method can be simplified and grow a high quality compound semiconductor layer rapidly, simply and inexpensively, as compared with a conventional ELO (Epitaxial Lateral Overgrowth) method or a method for forming a compound semiconductor layer on a metal layer. And, the metal layer serves as one electrode of a light emitting device and a light reflecting film to provide a light emitting device having reduced power consumption and high light emitting efficiency.

Abstract translation: 化合物半导体基板及其制造方法技术领域本发明涉及化合物半导体基板及其制造方法。 本发明提供一种制造方法，其在基板上涂布球形球，在球形球之间形成金属层，去除球形球以形成开口，并从开口生长化合物半导体层。 根据本发明，与传统的ELO（外延横向生长）方法或在金属上形成化合物半导体层的方法相比，可以简化和简单且廉价地生产高质量的化合物半导体层 层。 并且，金属层用作发光器件和光反射膜的一个电极，以提供具有降低的功率消耗和高发光效率的发光器件。

公开(公告)号：US20080102226A1

公开(公告)日：2008-05-01

申请号：US11663496

申请日：2005-09-22

Applicant: Ho-jun Lee ,  Dong-ryul Kim ,  Sang-uk Ryu ,  Hee-jung Kim

Inventor： Ho-jun Lee ,  Dong-ryul Kim ,  Sang-uk Ryu ,  Hee-jung Kim

IPC: C09K19/38

CPC classification number: G02F1/133634 ,  Y10T428/10

Abstract: The present invention relates to a polyarylate film having high level of negative phase difference toward out of plane direction, which is good enough to be used as an optical compensator film providing wide view angle. The polyarylate film prepared in the present invention has bigger birefringence toward out of plane direction than that of polymer for the conventional compensator film, suggesting that it not only reduces the thickness of the final product but also has the effect of optical compensation only with thin film coating.

Abstract translation: 本发明涉及一种具有高平面方向的负相位差高的多芳基化合物膜，其可以用作提供宽视角的光学补偿膜。 本发明制备的多芳基化合物膜对于常规的补偿膜具有比面向聚合物的平面外方向更大的双折射，这表明它不仅降低了最终产品的厚度，而且还具有仅用薄膜进行光学补偿的效果 涂层。

公开(公告)号：US20080032675A1

公开(公告)日：2008-02-07

申请号：US11835205

申请日：2007-08-07

Applicant: Ho-Jun LEE ,  Chul-Yong Jeon

Inventor： Ho-Jun LEE ,  Chul-Yong Jeon

IPC: H04M1/64

CPC classification number: H04M1/645 ,  H04M1/72566

Abstract: Disclosed are a method and a mobile terminal for outputting an automatic response message informing a caller of a user's (i.e. recipient's) current schedule when the user is unable to answer an incoming call. The method includes receiving an incoming call, determining whether an automatic response key is pressed to output an automatic response message with implementation of the schedule management function, detecting any schedule information corresponding to the current time by reference to a schedule management table when the automatic response key is pressed, and sending a schedule informing message including the detected schedule information to a caller's terminal.

Abstract translation: 公开了一种方法和移动终端，用于在用户不能应答呼入时输出通知呼叫者用户（即接收方）当前时间表的自动应答消息。 该方法包括接收来电，确定是否按照自动响应键输出自动响应消息，并执行日程管理功能，当自动响应时参考时间表管理表，检测与当前时间相对应的任何时间表信息 键，并向呼叫者的终端发送包括检测到的日程信息的调度通知消息。

公开(公告)号：US06914375B2

公开(公告)日：2005-07-05

申请号：US10158868

申请日：2002-06-03

Applicant: Ho Jun Lee

Inventor： Ho Jun Lee

IPC: H01J29/02 ,  H01J29/07 ,  H01J29/80 ,  H01J29/81

CPC classification number: H01J29/07 ,  H01J2229/0744

Abstract: Dynamic vibration absorber in a CRT having a shadow mask fastened to an inside surface of a panel by main frames, including a base part to be fitted to a non-effective surface of the shadow mask, and a vibration absorbing part having one end connected to the base part and the other end designed to make no contact with the shadow mask and the main frame, thereby attenuating vibration of the shadow mask.

Abstract translation: 具有通过主框架固定在面板内表面上的荫罩的CRT中的动态吸振体，包括要嵌入荫罩的非有效表面的基座部分和一端连接到 底座部分和另一端被设计成不与荫罩和主框架接触，从而衰减荫罩的振动。

公开(公告)号：US5810994A

公开(公告)日：1998-09-22

申请号：US725620

申请日：1996-10-03

Applicant: Ho Jun Lee ,  Choong Ki Kim ,  Chul Hi Han

Inventor： Ho Jun Lee ,  Choong Ki Kim ,  Chul Hi Han

IPC: B32B7/02 ,  C25F3/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3063 ,  H01L21/762 ,  H01L27/12

CPC classification number: C25F3/12 ,  H01L21/2007 ,  H01L21/76251

Abstract: A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.

Abstract translation: 绝缘体上硅器件晶片，具有均匀厚度的非常薄的单晶膜。 其通过通孔技术制造，其中在蚀刻装置中用基底硅蚀刻溶液蚀刻绝缘体上的单晶硅膜，通过以这样的方式施加通孔，使得该溶液可以用作阳极，并且SOI结构的衬底作为 一个阴极。 绝缘体的存在在单晶硅膜的下部区域和衬底中的电子产生空位，使得充满空位的下部区域不被基底硅蚀刻溶液除去，从而留下高度均匀的薄单晶硅 电影。