公开(公告)号：US11476858B2

公开(公告)日：2022-10-18

申请号：US17221166

申请日：2021-04-02

Applicant: Imec vzw

Inventor： Ewout Martens ,  Davide Dermit ,  Jan Craninckx

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/46

Abstract: An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.

公开(公告)号：US11476155B2

公开(公告)日：2022-10-18

申请号：US17237699

申请日：2021-04-22

Applicant: IMEC VZW

Inventor： Victor M. Blanco ,  Frederic Lazzarino

IPC: H01L21/768 ,  H01L21/033

Abstract: A method that provides patterning of an underlying layer to form a first set of trenches and a second set of trenches in the underlying layer is based on a combination of two litho-etch (LE) patterning processes supplemented with a spacer-assisted (SA) technique. The method uses one or more first upper blocks formed by a tone-inversion approach, an upper memorization layer allowing first memorizing upper trenches, and then second upper blocks, and a lower memorization layer allowing first memorizing first lower trenches and one or more first lower blocks, and then second lower trenches and one or more second lower blocks.

公开(公告)号：US11454583B2

公开(公告)日：2022-09-27

申请号：US17133771

申请日：2020-12-24

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R & D

Inventor： Chengxun Liu ,  Andim Stassen ,  Ying Ting Set

IPC: G01N15/10 ,  G01N15/00

Abstract: An example includes a field-flow fractionation device for the continuous separation of sample components including a channel comprising a sample inlet and a plurality of sample outlets, the channel being for coupling to a flow generator for translocating the sample components along the channel in a first direction from the sample inlet to the plurality of sample outlets, an actuator, which is not the flow generator, coupled to the channel, for translocating the sample components in a second direction, at a first angle with the first direction, an array of electrodes for connection to an AC power source, being in a path taken by the sample components in the channel, arranged in a plurality of rows, and in such a way that adjacent rows can be set at different potentials and every other row can be set at the same potential.

公开(公告)号：US20220300824A1

公开(公告)日：2022-09-22

申请号：US17639521

申请日：2020-09-04

Applicant: IMEC VZW ,  UNIVERSITEIT ANTWERPEN ,  UNIVERSITEIT GENT

Inventor： Adnan SHAHID ,  Jaron FONTAINE ,  Eli DE POORTER ,  Ingrid MOERMAN ,  Miguel Hernando CAMELO BOTERO ,  Steven LATRE

IPC: G06N3/08 ,  G06N3/04 ,  H04W48/16

Abstract: A computer-implemented method providing a neural network for identifying radio technologies employed in an environment. The neural network includes an autoencoder having an encoder, and a classifier. The method has the steps of sensing a radio spectrum of the environment thereby obtaining a set of data samples, labelling a subset of the data samples by a respective radio technology thereby obtaining labelled data samples, training the autoencoder in an unsupervised way by unlabelled data samples, training the classifier in a supervised way by the labelled data samples, and providing the neural network by coupling the output of an encoder network of the autoencoder to an input of the classifier.

公开(公告)号：US20220282197A1

公开(公告)日：2022-09-08

申请号：US17653070

申请日：2022-03-01

Applicant: IMEC VZW

Inventor： Candice M. Hovell ,  Jeremy Mares

IPC: C12M1/00 ,  F21V8/00 ,  C12M1/12 ,  C12M1/42 ,  C12M3/00

Abstract: The present disclosure relates to bioreactor tiles including fluidic channels and optical waveguides. One example system includes a substrate having a first channel, a second channel, and a third channel defined therein. The three channels are separated from one another by partial wall structures. The system also includes an optical waveguide configured to receive illumination light at a first end of the optical waveguide; propagate the illumination light toward a second end of the optical waveguide; allow at least a portion of the illumination light to escape the optical waveguide from a first surface of the optical waveguide as the illumination light propagates toward the second end of the optical waveguide; and provide the portion of the illumination light that escapes the optical waveguide from the first surface to the second channel or the third channel.

公开(公告)号：US11434424B2

公开(公告)日：2022-09-06

申请号：US17353092

申请日：2021-06-21

Applicant: IMEC VZW

Inventor： Guy Vereecke

IPC: C09K13/04 ,  C09K13/08 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213

Abstract: An aqueous solution for etching silicon dioxide and method of use are provided. The aqueous solution includes the anion F− in a concentration ranging from 2 to 4 mol/l and a cation of formula RR′R″R′″N+ in a concentration ranging from 1.5 to 2 mol/l, wherein each of R, R′, R″, and R′″ are independently selected from hydrogen and C1-5 alkyl chains with the proviso that the total number of carbon atoms in R, R′, R″, and R′″ combined equals from 8 to 16.

公开(公告)号：US20220254795A1

公开(公告)日：2022-08-11

申请号：US17650154

申请日：2022-02-07

Applicant: IMEC vzw

Inventor： Mihaela Ioana Popovici ,  Amey Mahadev Walke ,  Jan Van Houdt

IPC: H01L27/11507 ,  H01L49/02 ,  H01L29/78

Abstract: A ferroelectric device, for instance, a metal-ferroelectric-metal (MFM) capacitor, a ferroelectric random access memory (Fe-RAM), or a ferroelectric field effect transistor (FeFET), is provided. In one aspect, the ferroelectric device is based on hafnium zirconate (HZO). The ferroelectric device can include a first electrode and a second electrode, and a doped HZO layer, which is arranged between the first electrode and the second electrode. The doped HZO layer can include a ferroelectric layer and at least two non-zero remnant polarization charge states. The doped HZO layer can be doped with at least two different elements selected from the lanthanide series, or with a combination of at least one element selected from the lanthanide series and at least one rare earth element.

公开(公告)号：US11387248B2

公开(公告)日：2022-07-12

申请号：US16218271

申请日：2018-12-12

Applicant: IMEC vzw

Inventor： Antonio Arreghini

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/788 ,  H01L29/786 ,  H01L29/792 ,  H01L21/768 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/11524 ,  H01L27/1157

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to three-dimensional semiconductor devices. In one aspect, a method of manufacturing a three-dimensional (3D) semiconductor device includes providing a horizontal layer structure above a substrate and forming an opening that extends vertically through the horizontal layer structure to the substrate. The method additionally includes lining an inside vertical surface of the opening with a gate stack and lining the inside vertical surface of the opening having the gate stack formed thereon with a sacrificial material layer. The method additionally includes filling the opening with a filling material and removing the sacrificial material layer to form a recess. The method further includes forming the channel by epitaxially growing, in the recess, a channel material upwards from the substrate.

公开(公告)号：US20220214972A1

公开(公告)日：2022-07-07

申请号：US17565594

申请日：2021-12-30

Applicant: IMEC VZW

Inventor： Manu Komalan Perumkunnil ,  Geert Van der Plas

IPC: G06F12/0815 ,  G06F12/1027 ,  G06F12/0875

Abstract: Example embodiments relate to integrated circuits with 3D partitioning. One embodiment includes an integrated circuit. The integrated circuit includes a first integrated circuit layer that includes processing cores. The integrated circuit also includes a second integrated circuit layer that includes memory arrays associated with processing cores. Additionally, the integrated circuit includes an intermediate integrated circuit layer interconnected with the first and second integrated circuit layers and including memory control logic and interface circuitries for managing data exchange between the processing cores and the memory arrays.

公开(公告)号：US11381242B2

公开(公告)日：2022-07-05

申请号：US17063003

申请日：2020-10-05

Applicant: IMEC VZW

Inventor： Francky Catthoor ,  Edouard Giacomin ,  Juergen Boemmels ,  Julien Ryckaert

IPC: H03K19/17736 ,  H01L27/06

Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.