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公开(公告)号：US11764799B2
公开(公告)日：2023-09-19
申请号：US17569061
申请日：2022-01-05
Applicant: IMEC VZW
Inventor： Jan Craninckx , Ewout Martens
CPC classification number: H03M1/1215 , H03M1/1023 , H03M1/187 , H03M1/56 , H04N5/06 , H04N25/75 , H03M1/123
Abstract: Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.
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公开(公告)号：US12301242B2
公开(公告)日：2025-05-13
申请号：US18019308
申请日：2021-07-13
Applicant: Sony Semiconductor Solutions Corporation , IMEC VZW
Inventor： Keigo Bunsen , Ewout Martens , Davide Dermit , Jan Craninckx
Abstract: There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that of a least significant bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.
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公开(公告)号：US20250119153A1
公开(公告)日：2025-04-10
申请号：US18904738
申请日：2024-10-02
Applicant: IMEC VZW
Abstract: A signal sampling circuitry comprises: a plurality of sampling units receiving an input signal for time-interleaved sampling, each sampling unit comprising: a sampling capacitor having a first plate connected to an output of the sampling unit; a first plate switch between the first plate and a first reference voltage, a second plate switch between a second plate of the sampling capacitor and a second reference voltage; an input buffer for outputting a buffered input signal to the second plate; wherein the input buffer is connected to at least one power gating switch for powering down the input buffer.
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4.发明申请公开(公告)号：US20210344349A1
公开(公告)日：2021-11-04
申请号：US17221166
申请日：2021-04-02
Applicant: Imec vzw
Inventor： Ewout Martens , Davide Dermit , Jan Craninckx
IPC: H03M1/06
Abstract: An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.
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公开(公告)号：US20220271765A1
公开(公告)日：2022-08-25
申请号：US17569061
申请日：2022-01-05
Applicant: IMEC VZW
Inventor： Jan Craninckx , Ewout Martens
Abstract: Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.
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Patent Agency Ranking
公开(公告)号：US10574255B2
公开(公告)日：2020-02-25
申请号：US16181222
申请日：2018-11-05
Applicant: IMEC vzw
Inventor： Benjamin Hershberg , Jan Craninckx , Ewout Martens
Abstract: A multiplying digital-to-analog conversion circuit for use in an analog-to-digital converter is disclosed. In one aspect, the circuit comprises an input block including a capacitor and arranged for switchably connecting a first terminal of the capacitor to an input voltage signal during a first phase and to a fixed reference voltage during a second phase, a sub-analog-to-digital conversion circuit connected to a second terminal of the capacitor and arranged for quantizing a voltage on the capacitor during the second phase, a sub-digital-to-analog conversion circuit that receives the quantized version of the voltage and outputs an analog voltage derived from the quantized version, a feedback block including an amplifier connected to the second terminal of the capacitor and producing, at an amplifier output during a third phase, a residue signal corresponding to a combination of the input voltage signal and the analog voltage, and a feedback circuit.
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公开(公告)号：US10484000B2
公开(公告)日：2019-11-19
申请号：US16218916
申请日：2018-12-13
Applicant: IMEC vzw
Inventor： Ewout Martens , Benjamin Hershberg , Jan Craninckx
Abstract: A SAR DAC architecture is disclosed. In one aspect, the SAR DAC architecture uses two parallel DACs for performing a comparison and feedback simultaneously. While one DAC executes a feedback step, the output of the other DAC is used as input for a comparator. For fast operation, the comparator performs the comparison with a reference voltage that has a positive or negative offset from a mid-scale value. The sign of the offset is determined by a previous comparison step. As a result, the same delay can be used for each DAC feedback and comparison, reducing the total conversion time to the time needed for N comparisons for an N-bit architecture, which is a reduction of almost a factor of 2 compared to the conventional SAR architecture.
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公开(公告)号：US09800258B2
公开(公告)日：2017-10-24
申请号：US15373578
申请日：2016-12-09
Applicant: IMEC VZW
Inventor： Ewout Martens , Jan Craninckx
CPC classification number: H03M1/66 , H03M1/1009 , H03M1/1047 , H03M1/1061 , H03M1/1071 , H03M1/466 , H03M1/468
Abstract: The disclosure relates to a circuit for stabilizing a digital-to-analog converter reference voltage. One example embodiment is a circuit for stabilizing a voltage on a reference node. The circuit includes a digital-to-analog converter that includes an array of capacitors and arranged for: receiving an input voltage via an input node, receiving a voltage via a reference node and a digital-to-analog code via a controller node, and outputting a digital-to-analog output voltage. The circuit also includes a capacitive network on the reference node comprising a fixed capacitor arranged to be pre-charged to an external reference voltage and a variable capacitor arranged to be pre-charged to an external auxiliary voltage. Further, the circuit includes a measurement block. In addition, the circuit includes a calibration block arranged for determining an updated setting of the variable capacitor based on the digital-to-analog code and the measured voltage on the reference node.
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公开(公告)号：US12191880B2
公开(公告)日：2025-01-07
申请号：US18083823
申请日：2022-12-19
Applicant: IMEC VZW
Inventor： Ewout Martens , Jan Craninckx
Abstract: A slope analog-to-digital converter, ADC, comprises: an input unit comprising a sampling capacitor, wherein the input unit is configured to during an initial period obtain a sampled value of an analog input signal and, during a conversion period, hold the sampled value across the sampling capacitor; and a comparator configured to determine a most significant bit of the analog input signal during the initial period; wherein the ADC during the conversion period is configured to receive a slope signal and to be adapted based on the determined most significant bit such that the comparator is further configured to adaptively compare the sampled value and the slope signal for converting the sampled value to a digital representation.
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10.发明授权公开(公告)号：US11476858B2
公开(公告)日：2022-10-18
申请号：US17221166
申请日：2021-04-02
Applicant: Imec vzw
Inventor： Ewout Martens , Davide Dermit , Jan Craninckx
Abstract: An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.
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