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公开(公告)号：US12301242B2
公开(公告)日：2025-05-13
申请号：US18019308
申请日：2021-07-13
Applicant: Sony Semiconductor Solutions Corporation , IMEC VZW
Inventor： Keigo Bunsen , Ewout Martens , Davide Dermit , Jan Craninckx
Abstract: There is provided an analog-to-digital converter circuit including: a first converter circuit generating a first digital code by performing analog-to-digital conversion on the basis of an input voltage; a second converter circuit generating a second digital code by performing, on the basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than that of a least significant bit of the first converter circuit; an error detector detecting a conversion error of the analog-to-digital conversion on the basis of the first and second digital codes, thereby generating error data indicating a bit having a conversion error and the kind of the conversion error; and a calibration circuit estimating an error factor on the basis of the first and second digital codes and the error data, and performing calibration of a circuit relevant to the estimated error factor on the basis of an estimation result.
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2.发明申请公开(公告)号：US20210344349A1
公开(公告)日：2021-11-04
申请号：US17221166
申请日：2021-04-02
Applicant: Imec vzw
Inventor： Ewout Martens , Davide Dermit , Jan Craninckx
IPC: H03M1/06
Abstract: An successive approximation register analog-to-digital converter is provided. The successive approximation register analog-to-digital converter includes a digital-to-analog converter, a successive approximation register, a comparator, and a threshold voltage determining unit. In this context, the threshold voltage determining unit is configured to dynamically determine the threshold voltage of the comparator on the basis of the input signal of the digital-to-analog converter or the output signal of the comparator.
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公开(公告)号：US11128326B2
公开(公告)日：2021-09-21
申请号：US17098178
申请日：2020-11-13
Applicant: IMEC vzw , Vrije Universiteit Brussel
Inventor： Johan Nguyen , Khaled Khalaf , Pierre Wambacq , Jan Craninckx
Abstract: A digital radio-frequency (RF) circuitry is disclosed. In one aspect, the circuitry includes a digitally controlled amplifier configured to receive an RF input signal and a digital control signal, and to output an amplitude controlled output signal. The digitally controlled amplifier includes one or more common-source amplifying unit cells. A respective common-source amplifying unit cell includes a sources node connected to a switching circuitry controllable by the digital control signal so as to activate or deactivate the common-source amplifying unit cell. The switching circuitry comprises a first switch configured to connect the source node with a first power supply node and a second switch configured to connect the source node with a second power supply node when activating and deactivating, respectively, the common-source amplifying unit cell.
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公开(公告)号：US10230347B2
公开(公告)日：2019-03-12
申请号：US15217927
申请日：2016-07-22
Applicant: IMEC VZW , VRIJE UNIVERSITEIT BRUSSEL
Abstract: A system having a tunable impedance network and a method of tuning a tunable impedance network are disclosed. In one aspect, a telecommunications device comprises an electrical-balance duplexer (EBD) circuit coupled to at least one output node of a transmit path (TXin), an antenna, and at least one input node of a receive path (RXout), wherein the EBD circuit is configured to isolate the transmit path from the receive path by signal cancellation, and a balancing network (Zbal) as part of the EBD circuit. In one embodiment, the balancing network is an integrated tunable impedance network configured to provide an impedance that matches a target impedance (Zant) associated with the antenna at a first frequency and simultaneously at a second, different frequency. The network comprises a first portion and a second portion, the first portion reducing the influence of the tuning of the second portion at the first frequency. In some embodiments, the network preferably comprises no explicit resistors.
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公开(公告)号：US20170179976A1
公开(公告)日：2017-06-22
申请号：US15369777
申请日：2016-12-05
Applicant: IMEC VZW
Inventor： Jan Craninckx , Jonathan Borremans , Maarten De Bock
IPC: H03M3/00
CPC classification number: H03M3/458 , H03M1/00 , H03M1/12 , H03M1/365 , H03M3/30 , H03M3/322 , H03M3/39 , H03M3/496
Abstract: A circuit and a method for converting an analog signal to a digital value representation is disclosed. In one aspect, the circuit includes an incremental sigma-delta analog-to-digital converter (ADC). The circuit further includes a first input line for providing a primary analog signal representing a sensor measurement to the incremental sigma-delta ADC. The circuit further includes a second input line for providing a secondary analog signal to the incremental sigma-delta ADC. The incremental sigma-delta ADC receives the primary and secondary analog signals during a first period (TADC1) and a second period (TADC2), respectively. The circuit further includes a filter configured to weight the digital values in a sequence of digital values output by the incremental sigma-delta ADC, and to output a single digital value representing the sensor measurement.
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Patent Agency Ranking
公开(公告)号：US09349484B2
公开(公告)日：2016-05-24
申请号：US14808267
申请日：2015-07-24
Applicant: IMEC VZW
Inventor： Bob Verbruggen , Kazuaki Deguchi , Jan Craninckx
CPC classification number: G11C27/02 , H03M1/1245
Abstract: The present disclosure relates to a sample-and-hold circuit includes a transistor arranged for switching between a sample mode and a hold mode and a bootstrap circuit arranged for maintaining in the sample mode a voltage level between a source terminal and a gate terminal of the transistor independent of the voltage at the source terminal and arranged for switching off the transistor in the hold mode. The bootstrap circuit includes a bootstrap capacitance arranged for being precharged to a given voltage during the hold mode, the bootstrap capacitance being connected between the source terminal and the gate terminal during the sample mode. In one example, the bootstrap circuit comprises a switched capacitor charge pump for generating the given voltage.
Abstract translation: 本公开涉及一种采样和保持电路，包括：晶体管，被布置用于在采样模式和保持模式之间切换;以及自举电路，布置成用于在采样模式中保持源极端子和栅极端子之间的电压电平 晶体管与源极端子处的电压无关，并且被设置为在保持模式下关断晶体管。 引导电路包括自举电容，其布置成在保持模式期间被预充电到给定电压，自举电容在采样模式期间连接在源极端子和栅极端子之间。 在一个示例中，自举电路包括用于产生给定电压的开关电容器电荷泵。
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公开(公告)号：US11764799B2
公开(公告)日：2023-09-19
申请号：US17569061
申请日：2022-01-05
Applicant: IMEC VZW
Inventor： Jan Craninckx , Ewout Martens
CPC classification number: H03M1/1215 , H03M1/1023 , H03M1/187 , H03M1/56 , H04N5/06 , H04N25/75 , H03M1/123
Abstract: Example embodiments relate to time-interleaved analog-to-digital converters and conversion methods thereof. One embodiment includes a slope analog-to-digital converter. The slope analog-to-digital converter includes a sample and hold stage configured to sample an analog input signal at a sampling frequency. The slope analog-to-digital converter also includes a comparator downstream to the sample and hold stage configured to compare the analog input signal to a slope signal. Further, the slope analog-to-digital converter includes a digital logic configured to receive a counter value corresponding to a voltage level of the slope signal and to sample the counter value based upon the comparison, thereby generating a digital representation of the analog input signal based upon the comparison. The slope signal is asynchronous to the sampling frequency.
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公开(公告)号：US20210399685A1
公开(公告)日：2021-12-23
申请号：US17328181
申请日：2021-05-24
Applicant: IMEC VZW , VRIJE UNIVERSITEIT BRUSSEL
Inventor： Sehoon Park , Jan Craninckx , Pierre Wambacq , Davide Guermandi
Abstract: An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.
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9.发明申请公开(公告)号：US20210104976A1
公开(公告)日：2021-04-08
申请号：US17061147
申请日：2020-10-01
Applicant: IMEC VZW
Inventor： Nereo Markulic , Jan Craninckx , Miguel Glassee
Abstract: The method of calibrating a two-point modulation phase locked loop (PLL) comprises observing, between the loop filter and the second injection point, the loop control signal over at least one period of the first periodic control signal; generating, from the observed loop control signal, a distortion profile; and applying the distortion profile to the second periodic control signal before injecting the second periodic control signal in the PLL. Since, in the case of non-linearity in the controlled oscillator, the PLL output deviates from the ideally expected one, cancellation through the first injection point becomes imperfect disturbing the loop. This error pattern can be observed on the loop filter which allows to generate a distortion profile to distort the second periodic control signal for the next period of the modulation. This will mitigate the effects of the non-linearity of the oscillator.
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公开(公告)号：US10516423B2
公开(公告)日：2019-12-24
申请号：US15621214
申请日：2017-06-13
Applicant: IMEC VZW , VRIJE UNIVERSITEIT BRUSSEL
Inventor： Nereo Markulic , Jan Craninckx
IPC: H03C3/09 , H03C5/00 , H04B1/04 , H04L7/00 , H04B17/11 , H04L27/36 , H04L7/033 , H04L27/04 , H04L27/152
Abstract: A polar transmitter provided for transmitting a phase/frequency modulated and amplitude modulated transmit signal and a method for generating a transmit signal using a polar transmitter are described. An example polar transmitter comprises a phase locked loop for generating a phase/frequency modulated precursor of the transmit signal. The phase locked loop comprises at its input a phase error detection unit for detecting a phase error of the precursor fed back from the output of the phase locked loop to the phase error detection unit as a feedback signal. The polar transmitter comprises a digital amplitude modulator for amplitude modulation of the precursor, resulting in the transmit signal. The digital amplitude modulator is arranged within the phase locked loop for amplitude modulation of the precursor before being output by the PLL. The phase error detection unit is further provided for detecting the amplitude of the feedback signal.
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