公开(公告)号：US07212426B2

公开(公告)日：2007-05-01

申请号：US10957166

申请日：2004-09-30

申请人： Min-Gun Park ,  Jin-Yub Lee

发明人： Min-Gun Park ,  Jin-Yub Lee

IPC分类号： G11C13/00

CPC分类号： G11C16/08

摘要： A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

摘要翻译： 一种能够以扇区为单位随机输入/输出数据的闪存系统。 闪存系统包括闪存（单元阵列），缓冲存储器，随机数据输入/输出电路和控制电路。 随机数据输入/输出电路以缓冲存储器的扇区为单位接收数据，或以扇区为单位将数据输出到缓冲存储器。 控制电路控制在缓冲存储器和随机数据输入/输出电路之间输入/输出数据的次序和次数。

公开(公告)号：US20070019474A1

公开(公告)日：2007-01-25

申请号：US11480236

申请日：2006-06-30

申请人： Jin-Kook Kim ,  Jin-Yub Lee

发明人： Jin-Kook Kim ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A method of programming a flash memory device includes charging selection lines with a first voltage while applying program data to bit lines to during a bit line setup interval, then activating a block word line to electrically connect the selection lines to corresponding word lines, and then applying a second voltage, greater than the first voltage, to a selected one of the selection lines. Related devices are also disclosed,

摘要翻译： 一种对闪速存储器件进行编程的方法包括：在位线建立间隔期间将程序数据应用于位线，然后激活块字线以将选择线电连接到对应的字线，然后将第一电压充电选择线，然后 将大于第一电压的第二电压施加到所选择的选择线之一。 还公开了相关设备，

公开(公告)号：US06930919B2

公开(公告)日：2005-08-16

申请号：US10788738

申请日：2004-02-26

申请人： Jin-Yub Lee ,  Dong-Kyu Youn ,  Min-Gun Park

发明人： Jin-Yub Lee ,  Dong-Kyu Youn ,  Min-Gun Park

IPC分类号： G11C16/00 ,  G11C11/34 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/34 ,  G11C16/0483

摘要： A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided. An example NAND-type flash memory device includes a status cell array which has a plurality of status cells and stores data indicating erase/program statuses of the memory blocks, a data generation circuit which generates data indicating a program status of a selected memory block in response to a data input command and generates data indicating an erase status of a selected memory block in response to a block erase setup command, a first signal generation circuit which generates a block status write enable signal and a clock signal in response to either one of an erase command and a program command, a selection circuit which selects at least one of the status cells of the status cell array in response to a block address of the selected memory block, a write circuit which receives data from the data generation circuit in response to the clock signal during a program or erase operation and writes the received data in the selected status cell, and a control circuit which operates in response to a block status write enable signal from the first signal generation circuit and controls the write circuit so as to the store the data inputted to the write circuit in a selected status cell when an erase/program operation for the selected memory block is carried out.

摘要翻译： 提供了包括具有多个存储块的存储单元阵列的NAND型闪速存储器件。 示例性的NAND型闪速存储器件包括具有多个状态单元并且存储指示存储块的擦除/程序状态的数据的状态单元阵列，产生指示所选存储块的程序状态的数据的数据生成电路 响应于数据输入命令并响应于块擦除设置命令产生指示所选存储器块的擦除状态的数据，产生块状态写使能信号的第一信号生成电路和响应于 擦除命令和程序命令;响应于所选存储器块的块地址选择状态单元阵列的状态单元中的至少一个的选择电路;响应于从数据生成电路接收数据的写入电路 在编程或擦除操作期间将时钟信号写入所选择的状态单元中，并将所接收的数据写入所选择的状态单元，以及控制电路， 对来自第一信号发生电路的块状态写入使能信号进行控制，并且当执行用于所选择的存储器块的擦除/编程操作时，控制写入电路以将输入到写入电路的数据存储在所选择的状态单元中 。

公开(公告)号：US06731540B2

公开(公告)日：2004-05-04

申请号：US10222573

申请日：2002-08-15

申请人： Jin-Yub Lee ,  June Lee

发明人： Jin-Yub Lee ,  June Lee

IPC分类号： G11C700

CPC分类号： G11C16/08 ,  G11C16/0483

摘要： A NAND flash memory device includes a first and second memory blocks. A shared row selection circuit is provided between the first and second memory blocks, selectively or simultaneously selecting the first and second memory blocks, and transferring wordline voltages to a selected memory block by means in a multi-boosting manner.

摘要翻译： NAND闪存器件包括第一和第二存储器块。 共享行选择电路设置在第一和第二存储器块之间，选择性地或同时选择第一和第二存储器块，并且通过多重增强方式将字线电压传送到所选存储块。

公开(公告)号：US06510537B1

公开(公告)日：2003-01-21

申请号：US09370938

申请日：1999-08-09

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G11C2900

CPC分类号： G06F11/1008 ,  G06F2211/109

摘要： Disclosed is semiconductor memory device and a method for correcting a data error therein. The device comprises a memory cell array that stores a plurality of data bits and a plurality of check bits corresponding to the plurality of data bits. A read circuit is further provided that performs an operation of reading out the plurality of data bits and the plurality of check bits from the memory cell array. The semiconductor memory device further comprises error circuits for correcting a first error in the data bits of the first group and a second error in the data bits of the second group, respectively. The error circuit receives in parallel odd-numbered and even-numbered data and check bits read out from the memory cell array during a first cycle of a read mode of operation and generates first syndrome bits and second syndrome bits. During a second cycle of the read mode of operation, the circuit corrects the error in the odd-numbered data bits and the error in the even-numbered data bits responsive to the first and the second syndrome bits, respectively.

摘要翻译： 公开了半导体存储器件及其中的数据错误校正方法。 该装置包括存储单元阵列，该存储单元阵列存储与多个数据位对应的多个数据位和多个校验位。 还提供读取电路，其执行从存储单元阵列读出多个数据位和多个校验位的操作。 半导体存储器件还包括用于校正第一组的数据位中的第一误差和第二组的数据位中的第二误差的误差电路。 错误电路在读取操作模式的第一周期期间并行地接收奇数和偶数数据以及从存储单元阵列读出的校验位，并产生第一校正子位和第二校正子位。 在读取操作模式的第二周期期间，电路分别根据第一和第二校正子位校正奇数数据位中的误差和偶数数据位中的误差。

公开(公告)号：US06278636B1

公开(公告)日：2001-08-21

申请号：US09521168

申请日：2000-03-08

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C16/10

摘要： Disclosed herein is a nonvolatile semiconductor memory device which comprises a memory cell array, page buffers and Y-pass gate circuit. Each page buffer according to the present invention contains its latch which has a first current driving capacity during a sensing period of a read operation and a second current driving capacity during a data output period of the read operation. Similar adjustable current drive capacity is provided during a program operation of the memory device. Preferably, such additional current drive capacity is provided via dual parallel pull-up transistors provided within a data latch circuit corresponding with each bit line of the memory device. Provision of the second parallel transistor and associated gating eliminates the need for one of the prior art circuit inverters in the latch, thereby reducing layout space over-all within the page buffer circuit region of the device.

摘要翻译： 本文公开了一种非易失性半导体存储器件，其包括存储单元阵列，页缓冲器和Y遍门电路。 根据本发明的每个页缓冲器包含其锁存器，其在读操作的感测周期期间具有第一电流驱动能力，并且在读操作的数据输出周期期间具有第二电流驱动能力。 在存储器件的编程操作期间提供类似的可调电流驱动能力。 优选地，通过设置在对应于存储器件的每个位线的数据锁存电路内的双并联上拉晶体管提供这种额外的电流驱动能力。 提供第二并联晶体管和相关门控消除了对锁存器中的现有技术电路逆变器之一的需要，从而在设备的页缓冲器电路区域内全部减少布局空间。

公开(公告)号：US08929171B2

公开(公告)日：2015-01-06

申请号：US13571486

申请日：2012-08-10

申请人： June-Hong Park ,  Jin-Yub Lee

发明人： June-Hong Park ,  Jin-Yub Lee

IPC分类号： G11C11/4193 ,  G11C5/14 ,  G11C16/04 ,  G11C16/30 ,  G11C8/10

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C8/10 ,  G11C16/04 ,  G11C16/30

摘要： A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied.

摘要翻译： 非易失性存储器件包括电压供应控制器（VSC），用于检测电源电压的电平并响应于此产生第一内部电压。 当电源电压正常提供时，VSC提供等于外部高电压的第一内部电压，但是当电源电压异常供给时，VSC将第一内部电压提供到低于外部高电压的电平。

公开(公告)号：US20130114338A1

公开(公告)日：2013-05-09

申请号：US13571486

申请日：2012-08-10

申请人： JUNE-HONG PARK ,  JIN-YUB LEE

发明人： JUNE-HONG PARK ,  JIN-YUB LEE

IPC分类号： G11C5/14 ,  G11C16/30 ,  G11C16/04

CPC分类号： G11C5/145 ,  G11C5/147 ,  G11C8/10 ,  G11C16/04 ,  G11C16/30

摘要： A nonvolatile memory device includes a voltage supply controller (VSC) detecting a level of a power supply voltage and generating a first internal voltage in response thereto. The VSC provides the first internal voltage at a level equal to an external high voltage when a power supply voltage is normally supplied, but provides the first internal voltage at a level lower than the external high voltage when a power supply voltage is abnormally supplied.

摘要翻译： 非易失性存储器件包括电压供应控制器（VSC），用于检测电源电压的电平并响应于此产生第一内部电压。 当电源电压正常提供时，VSC提供等于外部高电压的第一内部电压，但是当电源电压异常供给时，VSC将第一内部电压提供到低于外部高电压的电平。

公开(公告)号：US08289770B2

公开(公告)日：2012-10-16

申请号：US12552738

申请日：2009-09-02

申请人： Jin-Yub Lee ,  Su-Chang Jeon

发明人： Jin-Yub Lee ,  Su-Chang Jeon

IPC分类号： G11C11/34

CPC分类号： G11C29/44 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2029/1208 ,  G11C2029/4402

摘要： A semiconductor memory device includes a memory core and a fail detection circuit. The memory core includes a memory cell array having a plurality of memory cells. The fail detection circuit compares read data with test data to generate a comparison signal representing whether each of the memory cells is failed or not, and accumulates and stores fail information of the memory cells corresponding to a plurality of addresses to output accumulated fail information. The read data are read out from the memory cells in which the test data are written.

摘要翻译： 半导体存储器件包括存储器芯和故障检测电路。 存储器核心包括具有多个存储单元的存储单元阵列。 失败检测电路将读取数据与测试数据进行比较以产生表示每个存储单元是否故障的比较信号，并且累积并存储与多个地址相对应的存储单元的故障信息以输出累积的故障信息。 从写入测试数据的存储单元读出读取的数据。

公开(公告)号：US08209460B2

公开(公告)日：2012-06-26

申请号：US10976384

申请日：2004-10-29

申请人： Jin-Yub Lee

发明人： Jin-Yub Lee

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C5/06 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C8/12

摘要： A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.

摘要翻译： 公开了一种双芯片封装，其包括至少两个存储器芯片，每个存储器芯片可以包含彼此具有不同地址系统的缓冲器和闪速存储器。 每个存储器芯片可以包括用于存储每个指示对应存储器芯片的选择的第一和第二标志信号的寄存器，用于将寄存器中的第一和第二标志信号与参考信号进行比较的比较器电路，以产生闪存访问信号和缓冲器 访问信号，以及用于响应于闪存访问信号和缓冲器访问信号来控制缓冲存储器和闪存的控制器。