公开(公告)号：US07545164B2

公开(公告)日：2009-06-09

申请号：US11540345

申请日：2006-09-29

Applicant: In Dal Song ,  Jung Bae Lee

Inventor： In Dal Song ,  Jung Bae Lee

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/017545 ,  H03K19/017581 ,  H04L25/0278 ,  H04L25/0286

Abstract: An output driver controls impedance using a mode register set. The output driver includes a main driving circuit that outputs and drives a main signal based on a data signal to a predetermined transmission line, an auxiliary driving circuit that outputs and drives an auxiliary signal to the transmission line, and a mode register set. The mode register set generates an impedance control signal group, a driving width control signal group and a delay control signal group. The amount of an auxiliary impedance (SIM), and the driving width and driving time point of an auxiliary signal (XSDR) can be controlled using the impedance control signal group, the driving width control signal group and the delay control signal group. Therefore, in accordance with the output driver of the present invention, the amount of output impedance (OIM), a pre-emphasis width and a pre-emphasis time point can be readily controlled, and the efficiency of the transmission of an output signal to a reception system is improved.

Abstract translation: 输出驱动器使用模式寄存器组控制阻抗。 输出驱动器包括：主驱动电路，其将基于数据信号的主信号输出并驱动到预定传输线;辅助驱动电路，其向传输线输出并驱动辅助信号;以及模式寄存器组。 模式寄存器组产生阻抗控制信号组，驱动宽度控制信号组和延迟控制信号组。 可以使用阻抗控制信号组，驱动宽度控制信号组和延迟控制信号组来控制辅助阻抗（SIM）的量以及辅助信号（XSDR）的驱动宽度和驱动时间点。 因此，根据本发明的输出驱动器，可以容易地控制输出阻抗（OIM）的量，预加重宽度和预加重时间点，并且输出信号的传输效率 改善了接收系统。

公开(公告)号：US07515486B2

公开(公告)日：2009-04-07

申请号：US11979496

申请日：2007-11-05

Applicant: Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

Inventor： Seong-young Seo ,  Jung-bae Lee ,  Byong-mo Moon

IPC: G11C7/10

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

公开(公告)号：US07440340B2

公开(公告)日：2008-10-21

申请号：US11252535

申请日：2005-10-18

Applicant: Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

Inventor： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

IPC: G11C5/14

CPC classification number: G11C7/1051 ,  G11C5/147 ,  G11C7/1048 ,  G11C7/1057

Abstract: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

Abstract translation: 数据输出缓冲器包括输出端子，缓冲器和下拉驱动器。 输出端耦合到传输线的第一端，传输线在第二端耦合到上拉终端电阻。 缓冲器将输出端上拉至第一电源电压，并根据输出数据信号将输出端拉低至第二电源电压。 下拉驱动器基于输出数据预先强调输出端子的下拉驱动操作的初始阶段。

公开(公告)号：US20080184002A1

公开(公告)日：2008-07-31

申请号：US11779349

申请日：2007-07-18

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F12/00 ,  G06F11/16

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

Abstract translation: 公开了一种存储器系统，存储器和存储器系统命令协议。 在存储器系统内，存储器控制器向存储器传送命令，该命令从包括写入命令和多个非写入命令的一组命令中选择。 在指示写入命令的数字值和指示多个非写入命令中的任何一个的数字值之间计算的汉明距离值大于1。

公开(公告)号：US20080181030A1

公开(公告)日：2008-07-31

申请号：US11862412

申请日：2007-09-27

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G11C7/00

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

公开(公告)号：US20080177949A1

公开(公告)日：2008-07-24

申请号：US12006766

申请日：2008-01-04

Applicant: Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

Inventor： Hoe-Ju Chung ,  Jung-Bae Lee ,  Joo-Sun Choi

IPC: G06F12/08

CPC classification number: G11C7/1075

Abstract: A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.

Abstract translation: 存储器系统基于堆栈位置信息选择性地设置信令模式。 存储器系统包括具有至少一个半导体存储器件和存储器控制器的存储器模块，该存储器控制器被配置为基于每个半导体存储器件的堆叠位置信息设置信号模式。 在差分信令模式中执行存储器控制器和每个半导体存储器件之间的信令，并且以单端信令模式执行半导体存储器件之间的信令。 因此，存储系统具有降低的功耗。

公开(公告)号：US20080106952A1

公开(公告)日：2008-05-08

申请号：US11979496

申请日：2007-11-05

Applicant: Seong-young SEO ,  Jung-bae LEE ,  Byong-mo MOON

Inventor： Seong-young SEO ,  Jung-bae LEE ,  Byong-mo MOON

IPC: G11C7/10

CPC classification number: G11C7/109 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1084

Abstract: A data buffer, such as a data strobe input buffer or a data input buffer, which may operate in multiple modes, such as a single mode (SM) and a dual mode (DM) and where the mode is selected by providing a signal, such as an external signal such as an address signal or an external command signal. A data buffer which can be used for a SM/DM dual-use and can improve a data setup/hold margin. A semiconductor memory device including one or more of the data buffers described above. A method for controlling propagation delay times which can improve a data setup/hold margin in a SM/DM dual-use data buffer.

Abstract translation: 诸如数据选通输入缓冲器或数据输入缓冲器的数据缓冲器，其可以以多种模式操作，例如单模（SM）和双模（DM），并且其中通过提供信号选择模式， 例如诸如地址信号或外部命令信号的外部信号。 一种可用于SM / DM两用的数据缓冲器，可以提高数据设置/保持余量。 一种包括上述数据缓冲器中的一个或多个的半导体存储器件。 一种用于控制传播延迟时间的方法，其可以改善SM / DM两用数据缓冲器中的数据建立/保持余量。

公开(公告)号：US20080102830A1

公开(公告)日：2008-05-01

申请号：US11873854

申请日：2007-10-17

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: H04Q7/32

CPC classification number: H04W48/16 ,  H04W8/183

Abstract: A method and an apparatus for connecting a network in a portable terminal. The method for connecting a network in a portable terminal includes searching a network from which a signal is received, receiving network identifying information from the searched network, retrieving connection information corresponding to the network identifying information, from network connection information stored in the portable terminal in advance, and setting the retrieved network connection information as the network connection information of the portable terminal.

Abstract translation: 一种用于连接便携式终端中的网络的方法和装置。 用于连接便携式终端中的网络的方法包括从存储在便携式终端中的网络连接信息中搜索从哪个接收到信号的网络，从所搜索的网络接收网络识别信息，检索与网络识别信息相对应的连接信息 提前，并将所检索的网络连接信息设置为便携式终端的网络连接信息。

公开(公告)号：US07295454B2

公开(公告)日：2007-11-13

申请号：US11225221

申请日：2005-09-12

Applicant: Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

Inventor： Chul-Woo Park ,  Sung-Hoon Kim ,  Hyuk-Joon Kwon ,  Jung-Bae Lee ,  Youn-Sik Park

IPC: G11C5/06

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract translation: 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US07164615B2

公开(公告)日：2007-01-16

申请号：US11169241

申请日：2005-06-27

Applicant: Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

Inventor： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。