公开(公告)号：US11575594B2

公开(公告)日：2023-02-07

申请号：US17016464

申请日：2020-09-10

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Jose Yallouz ,  Lion Levi ,  Tamir Ronen ,  Vladimir Koushnir ,  Neria Uzan

IPC: G06F15/16 ,  H04L45/00 ,  H04L41/12 ,  H04L45/48 ,  H04L12/44

Abstract: A computing system including network elements arranged in at least one group. A plurality of the network elements are designated as spines and another plurality are designated as leaves, the spines and leaves are interconnected in a bipartite topology, and at least some of the spines and leaves are configured to: receive in a first leaf, from a source node, packets destined to a destination node via a second leaf, forward the packets via a first link to a first spine and to the second leaf via a second link, in response to detecting that the second link has failed, apply a detour path from the first leaf to the second leaf, including a detour link in a spine-to-leaf direction and another detour link a leaf-to-spine direction, and forward subsequent packets, which are received in the first leaf and are destined to the second leaf, via the detour path.

公开(公告)号：US11516135B2

公开(公告)日：2022-11-29

申请号：US16746879

申请日：2020-01-19

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Niv Aibester ,  Aviv Kfir ,  Gil Levy ,  Liron Mula

IPC: H04L41/16 ,  H04L47/20 ,  H04L47/32 ,  H04L47/783 ,  H04L47/2441

Abstract: Apparatus for global policing of a bandwidth of a flow, the apparatus including a network device including a local policer configured to perform bandwidth policing on the flow within the network device, and a communications module configured to: send local policer state information from the local policer to a remote global policer, and receive policer state information from the remote global policer and update the local policer state information based on the remote global policer state information, Related apparatus and methods are also provided.

公开(公告)号：US20220269577A1

公开(公告)日：2022-08-25

申请号：US17182266

申请日：2021-02-23

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Vadim Gechman ,  Tamar Viclizki ,  Gaby Vanesa Diengott ,  David Slama ,  Samir Deeb ,  Shie Mannor ,  Gal Chechik

IPC: G06F11/34 ,  G06F11/30 ,  G06N20/00

Abstract: A method for data-center management includes, in a data center including multiple components, monitoring a plurality of performance measures of the components. A set of composite metrics is automatically defined, each composite metric including a respective weighted combination of two or more performance measures from among the performance measures. Baseline values are established for the composite metrics. An anomalous deviation is detected of one or more of the composite metrics from the respective baseline values.

公开(公告)号：US20220263776A1

公开(公告)日：2022-08-18

申请号：US17175716

申请日：2021-02-15

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Liron Mula ,  Idan Matari ,  Niv Aibester ,  George Elias ,  Lion Levi

IPC: H04L12/861 ,  H04L12/823

Abstract: A network device includes multiple ports, multiple buffer slices, a controller, and buffer control circuitry. The multiple ports are configured to communicate packets over a network. The multiple buffer slices are linked respectively to the multiple ports. The controller is configured to allocate a group of two or more of the buffer slices to a selected port among the ports. The buffer control circuitry is configured to buffer the packets, communicated via the selected port, in the group of the buffer slices, using zero-copy buffering.

公开(公告)号：US20220239071A1

公开(公告)日：2022-07-28

申请号：US17156970

申请日：2021-01-25

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Tali Septon ,  Itshak Kalifa ,  Elad Mentovich ,  Matan Galanty ,  Yaakov Gridish ,  Hanan Shumacher ,  Vadim Balakhovski ,  Juan Jose Vegas Olmos

IPC: H01S5/42 ,  H01S5/026 ,  H01S5/183

Abstract: A method and system for large scale Vertical-Cavity Surface-Emitting Laser (VCSEL) binning from wafers to be compatible with a Clock-Data Recovery Unit (CDRU) and/or a VCSEL driver are provided. An illustrative method of binning is provided that includes: for at least a portion of VCSELs on a wafer, measuring a set of representative parameters of the VCSELs, of predetermined DC or small-signal values, and sorting the measured VCSELs into clusters according to the measured set of representative parameters of the VCSELs; further sorting the clusters into sub-groups that comply with specifications of the VCSEL driver; and providing a feedback signal to the CDRU for equalizing control signals provided to the VCSEL driver.

公开(公告)号：US20220239056A1

公开(公告)日：2022-07-28

申请号：US17156902

申请日：2021-01-25

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Tali Septon ,  Itshak Kalifa ,  Elad Mentovich ,  Matan Galanty ,  Yaakov Gridish ,  Hanan Shumacher ,  Vadim Balakhovski ,  Juan Jose Vegas Olmos

IPC: H01S5/00

Abstract: A method and system for analyzing Vertical-Cavity Surface-Emitting Lasers (VCSELs) on a wafer are provided. An illustrative method of is provided that includes: applying a stimulus to each of the plurality of VCSELs on the wafer; measuring, for each of the plurality of VCSELs, two or more VCSEL parameters responsive to the stimulus; correlating the measured two or more VCSEL parameters to define a value of a common performance characteristic; and identifying clusters of VCSELs having similar values of the common performance characteristic. The clusters of VCSELs may be determined to collectively meet or not meet an optical performance requirement defined for the VCSELs on the wafer.

公开(公告)号：US20220131826A1

公开(公告)日：2022-04-28

申请号：US17079543

申请日：2020-10-26

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Lion Levi ,  Vladimir Koushnir ,  Matty Kadosh ,  Gil Bloch ,  Aviad Levy ,  Liran Liss ,  Dvir Libhaber

IPC: H04L29/12 ,  H04L12/751

Abstract: A router includes routing circuitry and a plurality of ports. The routing circuitry is configured to receive from a first subnetwork, via one of the ports, a packet destined to be delivered to a target node located in a second subnetwork, to select a mapping, from among two or more mappings, depending on a topological relation between the first subnetwork and the second subnetwork, to map a Layer-3 address of the packet into a Layer-2 address using the selected mapping, and to forward the packet via another one of the ports to the Layer-2 address.

公开(公告)号：US11303357B1

公开(公告)日：2022-04-12

申请号：US17194554

申请日：2021-03-08

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Avner Badihi

IPC: H04B10/25

Abstract: An optical device includes a chip, a set of waveguides on the chip and configured to carry first optical signals modulated with data during a data transmission stage, and an alignment waveguide on the chip. The alignment waveguide is configured to receive a second optical signal during an alignment stage that aligns the set of waveguides with a collimator including a set of lenses. The alignment waveguide is configured to output the second optical signal from the chip. The second optical signal output from the chip is indicative of a quality of alignment between the set of waveguides and the collimator.

公开(公告)号：US20210359943A1

公开(公告)日：2021-11-18

申请号：US17224208

申请日：2021-04-07

Applicant: MELLANOX TECHNOLOGIES TLV LTD.

Inventor： Gil Levy ,  Aviv Kfir ,  Matty Kadosh ,  Salvatore Pontarelli ,  Pedro Reviriego

IPC: H04L12/745 ,  H04L12/743 ,  H04L12/751 ,  H04L12/721 ,  H04L12/717

Abstract: In one embodiment, a packet processing apparatus includes interfaces, a memory to store a representation of a routing table as a binary search tree of address prefixes, and store a marker with an embedded prefix including k marker bits providing a marker for an address prefix of a node corresponding to a prefix length greater than k, and n additional bits, such that the k marker bits concatenated with the n additional bits provide another address prefix, packet processing circuitry configured upon receiving a data packet having a destination address, to traverse the binary search tree to find a longest prefix match, compare a key with the k marker bits, extract an additional n bits from the destination address, and compare the extracted n bits with the n additional bits, and process the data packet in accordance with a forwarding action indicated by the longest prefix match.

公开(公告)号：US20210336868A1

公开(公告)日：2021-10-28

申请号：US17368871

申请日：2021-07-07

Applicant: Mellanox Technologies TLV Ltd.

Inventor： Tamir Ronen ,  Yuval Shpigelman

IPC: H04L12/733 ,  G06F13/40 ,  H04L12/751 ,  H04L12/707 ,  H04L12/721 ,  H04L12/713

Abstract: An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.