公开(公告)号：US07743233B2

公开(公告)日：2010-06-22

申请号：US11100032

申请日：2005-04-05

Applicant: Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

Inventor： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

IPC: G06F9/00

CPC classification number: G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

Abstract translation: 公开了用于管理和转换逻辑定序器地址与多序列器多线程系统中的物理或逻辑顺控程序之间的映射的系统，方法和机制的实施例。 映射管理器可以管理逻辑顺控程序地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这样的映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：US20090172438A1

公开(公告)日：2009-07-02

申请号：US11964439

申请日：2007-12-26

Applicant: Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

Inventor： Arvind Kumar ,  Per Hammarlund ,  Glenn Hinton ,  Johan G. Van De Groenendaal

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3209 ,  Y02D10/171

Abstract: A low cost, low power consumption scalable architecture is provided to allow a computer system to be managed remotely during all system power states. In a lowest power state, power is only applied to minimum logic necessary to examine a network packet. Power is applied for a short period of time to an execution subsystem and one of a plurality of cores selected to handle processing of received service requests. After processing the received service requests, the computer system returns to the lowest power state.

Abstract translation: 提供了低成本，低功耗的可扩展架构，以允许在所有系统电源状态期间远程管理计算机系统。 在最低功率状态下，功率仅适用于检查网络分组所需的最小逻辑。 将电力短时间施加到执行子系统，并且被选择用于处理所接收的服务请求的处理的多个核心中的一个。 在处理接收到的服务请求之后，计算机系统返回到最低功率状态。

公开(公告)号：US07533247B2

公开(公告)日：2009-05-12

申请号：US11324143

申请日：2005-12-30

Applicant: Stephan Jourdan ,  Per Hammarlund ,  Alexandre Farcy ,  John Alan Miller

Inventor： Stephan Jourdan ,  Per Hammarlund ,  Alexandre Farcy ,  John Alan Miller

IPC: G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC classification number: G06F9/3802

Abstract: The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead of operations identified by the frame signature.

Abstract translation: 本主题涉及操作框架过滤，构建和执行。 一些实施例包括识别帧签名，计数帧签名的执行次数，以及构建要执行的操作帧，而不是由帧签名识别的操作。

公开(公告)号：US07516313B2

公开(公告)日：2009-04-07

申请号：US11027392

申请日：2004-12-29

Applicant: Bratin Saha ,  Matthew C. Merten ,  Sebastien Hily ,  David A. Koufaty ,  Per Hammarlund

Inventor： Bratin Saha ,  Matthew C. Merten ,  Sebastien Hily ,  David A. Koufaty ,  Per Hammarlund

IPC: G06F13/376 ,  G06F9/38 ,  G06F13/18

CPC classification number: G06F9/3851 ,  G06F9/526

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括用于预测在程序中要执行的操作的竞争的预测器。 可以基于预测的结果来处理该操作，该结果可以基于多个独立的预测。 在一个实施例中，如果没有预测到争用，则可以优化操作。 描述和要求保护其他实施例。

公开(公告)号：US20090089562A1

公开(公告)日：2009-04-02

申请号：US11904395

申请日：2007-09-27

Applicant: Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

Inventor： Ethan Schuchman ,  Hong Wang ,  Chris Weaver ,  Belliappa M. Kuttanna ,  Asit Mallick ,  Vivek K. De ,  Per Hammarlund

IPC: G06F9/312

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3265 ,  G06F1/3268 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30105 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/461 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/154 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.

Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。

公开(公告)号：US20070283129A1

公开(公告)日：2007-12-06

申请号：US11321022

申请日：2005-12-28

Applicant: Stephan Jourdan ,  Avinash Sodani ,  Michael Fetterman ,  Per Hammarlund ,  Glenn Hinton

Inventor： Stephan Jourdan ,  Avinash Sodani ,  Michael Fetterman ,  Per Hammarlund ,  Glenn Hinton

IPC: G06F15/00

CPC classification number: G06F9/3017 ,  G06F9/30036 ,  G06F9/30192 ,  G06F9/3836

Abstract: According to one embodiment, a method is disclosed. The method includes receiving a value at a vector length (VL) tracker and establishing a VL for subsequent micro-operations (μops) that are to be executed corresponding to the value.

Abstract translation: 根据一个实施例，公开了一种方法。 该方法包括：在向量长度（VL）跟踪器处接收一个值，并为对应于该值执行的后续微操作（muops）建立一个VL。

公开(公告)号：US20070156990A1

公开(公告)日：2007-07-05

申请号：US11323000

申请日：2005-12-30

Applicant: Per Hammarlund ,  Stephan Jourdan ,  Michael Fetterman ,  Glenn Hinton ,  Sebastien Hily ,  Ronak Singhal

Inventor： Per Hammarlund ,  Stephan Jourdan ,  Michael Fetterman ,  Glenn Hinton ,  Sebastien Hily ,  Ronak Singhal

IPC: G06F13/00

CPC classification number: G06F9/30043 ,  G06F9/30032

Abstract: A method is disclosed. The method includes scheduling a load operation at least twice the size of a maximum access supported by a memory device, dividing the load operation into a plurality of separate load operation segments having a size equivalent to the maximum access supported by the memory device, and performing each of the plurality of load operation segments. A further method is disclosed where a temporary register is used to minimize the number of memory accesses to support unaligned accesses.

Abstract translation: 公开了一种方法。 该方法包括将加载操作调度至少是由存储器件支持的最大访问大小的两倍，将加载操作划分成具有等于存储器设备支持的最大访问大小的多个单独的加载操作段，以及执行 多个加载操作段中的每一个。 公开了一种另外的方法，其中使用临时寄存器来最小化用于支持未对齐访问的存储器访问的数量。

公开(公告)号：US20070143575A1

公开(公告)日：2007-06-21

申请号：US11315964

申请日：2005-12-21

Applicant: Stephen Jourdan ,  Per Hammarlund ,  Michael Fetterman ,  Michael Cornaby ,  Glenn Hinton ,  Avinash Sodani

Inventor： Stephen Jourdan ,  Per Hammarlund ,  Michael Fetterman ,  Michael Cornaby ,  Glenn Hinton ,  Avinash Sodani

IPC: G06F15/00

CPC classification number: G06F9/345 ,  G06F9/3017 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3844

Abstract: In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instruction to operate on a vector if the instruction is predicted to be unmasked and unit-stride, the instruction to access elements in memory, and accessing via the optimized μop flow two or more of the elements at the same time without determining masks of the two or more elements. Other embodiments are also described.

Abstract translation: 在一个实施例中，公开了一种用于向量流单个指令，多数据（SIMD）扩展（VSSE）存储器操作的流优化和预测的方法。 该方法包括：如果预测指令是未屏蔽和单步的，则生成用于对矢量进行操作的指令的优化的微操作（muop）流程，访问存储器中的元件的指令以及经由优化的muop流2访问 或更多的元素，而不确定两个或更多个元件的掩模。 还描述了其它实施例。

公开(公告)号：US20070101076A1

公开(公告)日：2007-05-03

申请号：US11263628

申请日：2005-10-31

Applicant: Martin Dixon ,  Michael Cornaby ,  Michael Fetterman ,  Per Hammarlund

Inventor： Martin Dixon ,  Michael Cornaby ,  Michael Fetterman ,  Per Hammarlund

IPC: G06F12/16

CPC classification number: G06F9/463 ,  G06F11/1438 ,  G06F11/2033

Abstract: In one embodiment, the present invention includes a method for requesting an allocation of memory to be a backing store for architectural state information of a processor and storing the architectural state information in the backing store using an application. In this manner, the backing store and processor enhancements using information in the backing store may be transparent to an operating system. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于请求分配作为用于处理器的体系结构状态信息的后备存储器的存储器并使用应用程序将架构状态信息存储在后备存储器中的方法。 以这种方式，使用后备存储器中的信息的后备存储和处理器增强可能对操作系统是透明的。 描述和要求保护其他实施例。

公开(公告)号：US07213093B2

公开(公告)日：2007-05-01

申请号：US10608708

申请日：2003-06-27

Applicant: Per Hammarlund ,  James B. Crossland ,  Anil Aggarwal ,  Shivnandan D. Kaushik

Inventor： Per Hammarlund ,  James B. Crossland ,  Anil Aggarwal ,  Shivnandan D. Kaushik

IPC: G06F12/14 ,  G06F9/46 ,  G06F13/00

CPC classification number: G06F9/526 ,  G06F1/3203 ,  G06F9/3004 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3851

Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.