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公开(公告)号:US10199505B2
公开(公告)日:2019-02-05
申请号:US15620444
申请日:2017-06-12
发明人: John H. Zhang
IPC分类号: H01L29/786 , H01L29/775 , H01L29/66 , H01L29/40 , H01L29/417 , H01L29/778 , H01L29/41 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/12 , H01L29/423 , H01L29/45 , H01L29/49 , H01L29/165
摘要: Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
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92.
公开(公告)号:US20190034150A1
公开(公告)日:2019-01-31
申请号:US16045269
申请日:2018-07-25
发明人: Benedetto VIGNA , Mahesh CHOWDHARY , Matteo DAMENO
摘要: A method includes receiving, at a master agent, announcements from candidate consumer agents indicating the presence of the candidate consumer agents. Each announcement includes display parameters for a display of the corresponding candidate consumer agent. The method further includes receiving at the master agent content parameters from a producer agent, the content parameters defining characteristics of content to be provided by the consumer agent. A mosaic screen is configured based on the received announcements and the content parameters. This configuring of the mosaic screen includes selecting ones of the consumer agents for which an announcement was received and generating content distribution parameters based on the content parameters and the display parameters of the selected ones of the consumer agents. The generated content distribution parameters are provided to the consumer agent.
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公开(公告)号:US10177255B2
公开(公告)日:2019-01-08
申请号:US15723152
申请日:2017-10-02
发明人: Pierre Morin , Nicolas Loubet
IPC分类号: H01L29/00 , H01L29/78 , H01L29/66 , H01L29/165 , H01L27/088
摘要: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
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94.
公开(公告)号:US10170475B2
公开(公告)日:2019-01-01
申请号:US15448626
申请日:2017-03-03
发明人: Stephane Allegret-Maret , Kangguo Cheng , Bruce Doris , Prasanna Khare , Qing Liu , Nicolas Loubet
IPC分类号: H01L29/66 , H01L27/092 , H01L27/11 , H01L21/8238 , H01L21/84 , H01L29/786 , H01L21/02 , H01L21/265 , H01L21/3065 , H01L21/311 , H01L21/762 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/165 , H01L29/417
摘要: An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.
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公开(公告)号:US10153371B2
公开(公告)日:2018-12-11
申请号:US14175215
申请日:2014-02-07
发明人: Xiuyu Cai , Qing Liu , Ruilong Xie
摘要: A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material.
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公开(公告)号:US20180344186A1
公开(公告)日:2018-12-06
申请号:US16041140
申请日:2018-07-20
发明人: John H. ZHANG
IPC分类号: A61B5/04 , A61B5/00 , B82Y30/00 , G01N27/414
CPC分类号: A61B5/04001 , A61B5/6877 , A61B5/688 , B82Y30/00 , G01N27/4145 , Y10T29/4913
摘要: It is recognized that, because of its unique properties, graphene can serve as an interface with biological cells that communicate by an electrical impulse, or action potential. Responding to a sensed signal can be accomplished by coupling a graphene sensor to a low power digital electronic switch that is activatable by the sensed low power electrical signals. It is further recognized that low power devices such as tunneling diodes and TFETs are suitable for use in such biological applications in conjunction with graphene sensors. While tunneling diodes can be used in diagnostic applications, TFETs, which are three-terminal devices, further permit controlling the voltage on one cell according to signals received by other cells. Thus, by the use of a biological sensor system that includes graphene nanowire sensors coupled to a TFET, charge can be redistributed among different biological cells, potentially with therapeutic effects.
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公开(公告)号:US10141246B2
公开(公告)日:2018-11-27
申请号:US15952068
申请日:2018-04-12
发明人: Jefferson Talledo , Tito Mangaoang
摘要: The present disclosure is directed to a leadframe package having a side solder ball contact and methods of manufacturing the same. A plurality of solder balls are coupled to recesses in a leadframe before encapsulation and singulation. After singulation, a portion of each solder ball is exposed on sidewalls of the package. This ensures that the sidewalls of the leads are solder wettable, which allows for the formation of stronger joints when the package is coupled to a substrate. This increased adhesion reduces resistance at the joints and also mitigates the effects of expansion of the components in the package such that delamination is less likely to occur. As a result, packages with a side solder ball contact have increased life cycle expectancies.
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公开(公告)号:US10134898B2
公开(公告)日:2018-11-20
申请号:US14982052
申请日:2015-12-29
发明人: Jocelyne Gimbert
IPC分类号: H01L29/78 , H01L21/265 , H01L21/324 , H01L21/70 , H01L21/8238 , H01L21/84 , H01L27/12 , H01L29/16 , H01L29/161 , H01L29/66 , H01L29/165
摘要: Methods and structures for forming highly-doped, ultrathin layers for transistors formed in semiconductor-on-insulator substrates are described. High dopant concentrations may be achieved in ultrathin semiconductor layers to improve device characteristics. Ion implantation at elevated temperatures may mitigate defect formation for stoichiometric dopant concentrations up to about 30%. In-plane stressors may be formed adjacent to channels of transistors formed in ultrathin semiconductor layers.
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99.
公开(公告)号:US10134759B2
公开(公告)日:2018-11-20
申请号:US14182601
申请日:2014-02-18
发明人: Nicolas Loubet , James Kuss
IPC分类号: H01L21/8238 , H01L27/12 , H01L27/092 , H01L21/84 , H01L29/16 , H01L29/161 , H01L29/06 , H01L29/786 , H01L21/02
摘要: A method for making a semiconductor device may include forming, above a substrate, a plurality of fins, forming a first semiconductor material on sides of a first group of the fins, and forming a second semiconductor material on sides of a second group of the fins. The method may further include forming a dielectric layer overlying the plurality of fins to define first and second groups of nanowires within the dielectric layer, with the first group of nanowires including the first semiconductor material and the second group of nanowires including the second semiconductor material.
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公开(公告)号:US20180331106A1
公开(公告)日:2018-11-15
申请号:US16035441
申请日:2018-07-13
发明人: Pierre Morin , Nicolas Loubet
IPC分类号: H01L27/092 , H01L29/66 , H01L29/10 , H01L29/16 , H01L29/78 , H01L29/165
CPC分类号: H01L27/0924 , H01L29/1054 , H01L29/16 , H01L29/1608 , H01L29/165 , H01L29/66636 , H01L29/66795 , H01L29/7843 , H01L29/7848 , H01L29/7849 , H01L29/785
摘要: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
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