公开(公告)号：US20110310659A1

公开(公告)日：2011-12-22

申请号：US13109157

申请日：2011-05-17

申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

IPC分类号： G11C11/24 ,  H03B5/12 ,  H03B7/06

CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

公开(公告)号：US08045663B2

公开(公告)日：2011-10-25

申请号：US12029518

申请日：2008-02-12

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

IPC分类号： H04L7/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.

摘要翻译： 数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。 使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。 偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。 定时控制单元通过发送侧接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与发送输出单元的发送采样时钟信号之间的定时 结果。 可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

公开(公告)号：US20110242924A1

公开(公告)日：2011-10-06

申请号：US13078218

申请日：2011-04-01

申请人： Dong-Min KIM ,  Young-Soo SOHN ,  Seung-Jun BAE ,  Kwang-Il PARK

发明人： Dong-Min KIM ,  Young-Soo SOHN ,  Seung-Jun BAE ,  Kwang-Il PARK

IPC分类号： G11C8/10

CPC分类号： G11C8/12 ,  G11C8/18

摘要： A semiconductor memory device includes a memory cell array, an address control unit and a logic circuit. The memory cell array includes a plurality of banks which are divided into a first bank block and a second bank block. The address control unit accesses the memory cell array. The logic circuit controls the address control unit based on a command and an address signal such that the first and second bank blocks commonly operate in a first operation mode, and the first and second bank blocks individually operate in a second operation mode.

摘要翻译： 半导体存储器件包括存储单元阵列，地址控制单元和逻辑电路。 存储单元阵列包括被划分成第一存储块和第二存储块的多个存储体。 地址控制单元访问存储单元阵列。 逻辑电路基于命令和地址信号控制地址控制单元，使得第一和第二存储体块以第一操作模式共同操作，并且第一和第二存储体块以第二操作模式分别操作。

公开(公告)号：US07957497B2

公开(公告)日：2011-06-07

申请号：US11938810

申请日：2007-11-13

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： H04L7/00

CPC分类号： H04L7/0337

摘要： A clock and data recovery (CDR) circuit comprises a data sampling unit which latches serial data input in response to data clock signals, and outputs a plurality of sampling data, the data clock signals maintaining a constant phase difference and having mutually different phases, an edge sampling unit which outputs an edge sampling signal generated by sampling edge information of the serial data in response to a selection edge clock signal, the selection edge clock signal being randomly selected from among a plurality of edge clock signals, a data selection unit which selects at least two consecutive sampling data from among the plurality of sampling data, and a decoding unit which performs a logical operation of the sampling data selected by the data selection unit and the edge sampling signal.

摘要翻译： 时钟和数据恢复（CDR）电路包括数据采样单元，其响应于数据时钟信号锁存串行数据输入，并输出多个采样数据，数据时钟信号维持恒定的相位差并具有相互不同的相位， 边缘采样单元，其响应于选择边沿时钟信号输出通过对串行数据的边缘信息进行采样而产生的边缘采样信号，从多个边缘时钟信号中随机选择选择边沿时钟信号;数据选择单元，其选择 来自多个采样数据中的至少两个连续采样数据，以及执行由数据选择单元选择的采样数据和边缘采样信号的逻辑运算的解码单元。

公开(公告)号：US20110044123A1

公开(公告)日：2011-02-24

申请号：US12939288

申请日：2010-11-04

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US20110029697A1

公开(公告)日：2011-02-03

申请号：US12902328

申请日：2010-10-12

申请人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

发明人： Jin-gook Kim ,  Kwang-il Park ,  Seung-jun Bae

IPC分类号： G06F3/00

CPC分类号： G11C5/063 ,  G06F1/10 ,  G11C7/1045 ,  G11C7/22 ,  G11C7/225 ,  G11C11/4076 ,  G11C2207/105

摘要： A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

摘要翻译： 存储器件被配置为在第一和第二数据输入/输出模式下操作。 存储器件包括第一电极焊盘，第二电极焊盘，时钟信号线，第一切换单元和第二转换单元。 时钟信号线被配置为将时钟传送到存储器件内部的集成电路。 第一开关单元响应于针对第一数据输入/输出模式发生的控制信号而切换以电连接第一电极焊盘和时钟信号线。 第二开关单元响应于针对第二数据输入/输出模式发生的控制信号的反相信号而切换以电连接第二电极焊盘和时钟信号线。

公开(公告)号：US07852706B2

公开(公告)日：2010-12-14

申请号：US12635751

申请日：2009-12-11

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-Jin Jang

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

摘要： A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

摘要翻译： 一种用于消除半导体存储器件和存储器控制器之间的接口中的数据与时钟信号之间的偏斜的电路，包括存储从半导体存储器件输出的边沿信息的边缘信息存储单元，伪数据模式生成单元，其输出伪 数据，包括与实际发送的数据类似的模式;相位检测单元，其从边缘信息存储单元接收边缘信息，并从伪数据模式产生单元接收伪数据，以检测数据和时钟信号之间的相位差，并产生 相应的检测结果，以及相位控制单元，其根据来自相位检测单元的相应检测结果控制时钟信号的相位，以便消除数据写入和读取操作中的每数据输入/输出引脚偏移 的半导体存储器件。

公开(公告)号：US07768429B2

公开(公告)日：2010-08-03

申请号：US12367134

申请日：2009-02-06

申请人： Seung-Jun Bae ,  Seong-Jin Jang

发明人： Seung-Jun Bae ,  Seong-Jin Jang

IPC分类号： H03M5/00

CPC分类号： H03M5/145

摘要： DC balance encoded data is transmitted by transmitting a preamble of dummy data that is configured to provide an intermediate number of bits of a given logic value that is at least one bit of the given logic value but less than a maximum number of bits of the given logic value in the DC balance encoded data, to thereby reduce the simultaneous switching noise that is caused by transmission of a first word of DC balance encoded data. The preamble may contain one or more words of fixed and/or variable dummy data.

摘要翻译： 通过发送伪数据的前导码来发送DC平衡编码数据，该伪数据的前导码被配置为提供给定逻辑值的中间位数，该给定逻辑值是给定逻辑值的至少一位，但小于给定逻辑值的最大位数 DC平衡编码数据中的逻辑值，从而减少由DC平衡编码数据的第一字的传输引起的同时开关噪声。 前导码可以包含固定和/或可变虚拟数据的一个或多个单词。

公开(公告)号：US20100141311A1

公开(公告)日：2010-06-10

申请号：US12627730

申请日：2009-11-30

申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

IPC分类号： H03L7/06 ,  H03K3/01

CPC分类号： H03L7/08

摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

公开(公告)号：US07701257B2

公开(公告)日：2010-04-20

申请号：US11870482

申请日：2007-10-11

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C11/4093

摘要： The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched digital control signals in the conventional art. In addition, embodiments of the invention implement each equalizer with a single sense amplifier based flip flop (SAFF) to reduce circuit size and power consumption.

摘要翻译： 本发明涉及诸如在半导体器件中使用的数据接收器。 本发明的实施例提供一种循环展开的DFE接收机，其使用来自每个均衡器的模拟控制信号来避免与传统技术中使用锁存的数字控制信号相关联的定时延迟。 此外，本发明的实施例用基于单个读出放大器的触发器（SAFF）来实现每个均衡器以减小电路尺寸和功耗。