Variable valve timing control device
    91.
    发明申请
    Variable valve timing control device 审中-公开
    可变气门正时控制装置

    公开(公告)号:US20060207537A1

    公开(公告)日:2006-09-21

    申请号:US11357087

    申请日:2006-02-21

    IPC分类号: F01L1/34

    摘要: A variable valve timing control device includes a housing member, a rotor member assembled on the housing member so as to rotate relative thereto, a vane provided on the rotor member, a fluid pressure chamber divided into an advanced angle chamber and a retarded angle chamber by the vane, a lock mechanism for restricting or allowing a relative rotation between the housing member and the rotor member by a lock member, a fluid pressure circuit for controlling an operation fluid to be supplied to or discharged from the advanced angle chamber, the retarded angle chamber, and the lock mechanism, a plate provided on the housing member and integrally rotating with the housing member, an engaging groove formed on the plate, and a contacting member arranged in the engaging groove so as to rotate integrally with the plate and engaging with a coupling member so as to be assembled thereon.

    摘要翻译: 一种可变气门正时控制装置,包括壳体构件,组装在壳体构件上以相对于其旋转的转子构件,设置在转子构件上的叶片,被分为前进角室和延迟角室的流体压力室, 叶片,用于通过锁定构件限制或允许壳体构件和转子构件之间的相对旋转的锁定机构,用于控制要从提前角室供给或排出的操作流体的流体压力回路,延迟角 所述锁定机构,设置在所述壳体部件上并与所述壳体部件一体旋转的板,形成在所述板上的接合槽,以及设置在所述接合槽中以使其与所述板一体旋转并与 联接构件,以便组装在其上。

    Valve timing control device
    95.
    发明授权
    Valve timing control device 有权
    气门正时控制装置

    公开(公告)号:US06782854B2

    公开(公告)日:2004-08-31

    申请号:US10649619

    申请日:2003-08-28

    IPC分类号: F01L134

    摘要: A valve timing control device includes a rotation member for opening and closing values, a rotation transmitting member rotatably mounted on the rotation member, a fluid chamber defined between the rotation member and the rotation transmitting member, a vane fitted into a vane groove formed on the rotation member or the rotation transmitting member so as to divide the fluid chamber into a advance angle pressure chamber and a retard angle pressure chamber, the vane groove having contacting portions contacted with the vane and an elastic member disposed between the vane and the rotation member or the rotation transmitting member, wherein the radial length between the bottom portion of the vane groove and a bottom portion side end portion of the contacting portion is larger than a radial length between the bottom portion of the vane groove and an engaging portion of the vane engaged with the elastic member.

    摘要翻译: 气门正时控制装置包括用于打开和关闭数值的旋转构件,可旋转地安装在旋转构件上的旋转传递构件,限定在旋转构件和旋转传递构件之间的流体室,安装在形成在旋转构件 旋转构件或旋转传递构件,以便将流体室分成提前角压力室和延迟角压力室,叶片槽具有与叶片接触的接触部分和设置在叶片和旋转构件之间的弹性构件, 旋转传递部件,其中,所述叶片槽的底部与所述接触部的底部侧端部之间的径向长度大于所述叶片槽的底部与所述叶片的接合部之间的径向长度, 与弹性构件。

    Data transfer system using memory with FIFO structure
    96.
    发明授权
    Data transfer system using memory with FIFO structure 失效
    数据传输系统采用FIFO结构的存储器

    公开(公告)号:US5608388A

    公开(公告)日:1997-03-04

    申请号:US543769

    申请日:1995-10-16

    申请人: Shigeru Nakajima

    发明人: Shigeru Nakajima

    摘要: A data transmission system includes control units connected to a network line and various sensors. Each of the control units includes an ID code comparing/processing section. In each of the ID code comparing/processing sections, multiplex communication control units, FIFO memory, CPU, main register and data extracting circuit are provided. Each of the multiplex communication control units receives an ID code extracted from a data frame transmitted via the network line by the data extracting circuit and checks whether the received ID code coincides with preset ID codes or not. The FIFO memory receives and holds the ID code in response to a coincidence signal from the multiplex communication control units and outputs a signal indicating that the ID code is held. The CPU detects that an ID code attached to main data necessary in the ID code comparing/processing section is input from the network line in response to a signal indicating that the ID code is held, processes main data stored in the main register corresponding to the ID code held in the FIFO memory.

    摘要翻译: 数据传输系统包括连接到网络线路和各种传感器的控制单元。 每个控制单元包括ID码比较/处理部分。 在每个ID码比较/处理部分中,提供了多路复用通信控制单元,FIFO存储器,CPU,主寄存器和数据提取电路。 每个复用通信控制单元从数据提取电路接收经由网络线发送的数据帧提取的ID码,并检查接收的ID码是否与预置的ID码一致。 FIFO存储器响应于来自多路复用通信控制单元的一致信号而接收并保持ID码,并输出表示该ID代码被保持的信号。 CPU检测到响应于指示保持了ID码的信号,从网络线输入附加到ID码比较/处理部分所需的主数据的ID代码,处理存储在主寄存器中对应的主寄存器的主数据 ID代码保存在FIFO存储器中。

    Field effect transistor having a spacer layer with different material
and different high frequency characteristics than an electrode supply
layer thereon
    97.
    发明授权
    Field effect transistor having a spacer layer with different material and different high frequency characteristics than an electrode supply layer thereon 失效
    场效应晶体管具有与其上的电极供应层不同的材料和不同的高频特性的间隔层

    公开(公告)号:US5473177A

    公开(公告)日:1995-12-05

    申请号:US180479

    申请日:1994-01-12

    申请人: Shigeru Nakajima

    发明人: Shigeru Nakajima

    CPC分类号: H01L29/7783

    摘要: There is disclosed a field effect transistor having a channel layer, an electron supply layer, and a spacer layer formed between the channel layer and the electron supply layer. The spacer layer has a thickness for spatially separating a two-dimensional electron gas from donor ions in the electron supply layer, and for forming the two-dimensional electron gas in the channel layer by the Coulomb force of the donor ions. The spacer layer material has better high frequency characteristics than that of the electron supply layer.

    摘要翻译: 公开了一种场效应晶体管,其具有沟道层,电子供应层和形成在沟道层和电子供应层之间的间隔层。 间隔层具有用于在电子供给层中空间分离二维电子气体与供体离子的厚度,并且通过供体离子的库仑力在沟道层中形成二维电子气。 间隔层材料具有比电子供给层更好的高频特性。

    Field effect transistor
    98.
    发明授权
    Field effect transistor 失效
    场效应晶体管

    公开(公告)号:US5436470A

    公开(公告)日:1995-07-25

    申请号:US818537

    申请日:1992-01-09

    申请人: Shigeru Nakajima

    发明人: Shigeru Nakajima

    CPC分类号: H01L29/8128

    摘要: The invention provides a FET by forming a channel layer in layer including "n" type impurity at high concentration, which is sandwiched by a first semiconductor layer and a second semiconductor layer lightly doped with impurity. Therefore even when electrons in the channel layer obtain high energy, the electrons in this arrangement rush out essentially to the second semiconductor layer excelling in electron carrying characteristic, thus a travelling speed of the electrons in the channel layer is not lowered. Furthermore the channel layer being formed in layer and allowed to include impurity at high concentration, the current drive capability can be improved.

    摘要翻译: 本发明通过在由第一半导体层和轻掺杂杂质的第二半导体层夹在高浓度的“n”型杂质的层中形成沟道层来提供FET。 因此,即使在沟道层中的电子获得高能量的情况下,该配置中的电子基本上突出到具有优异的电子携带特性的第二半导体层,因此沟道层中的电子的移动速度不降低。 此外,沟道层形成为层并允许包含高浓度的杂质,可以提高电流驱动能力。

    Field-effect transistor having a double pulse-doped structure
    99.
    发明授权
    Field-effect transistor having a double pulse-doped structure 失效
    具有双脉冲掺杂结构的场效应晶体管

    公开(公告)号:US5408111A

    公开(公告)日:1995-04-18

    申请号:US025410

    申请日:1993-02-26

    摘要: A buffer layer, a first undoped layer, a first active layer and second undoped layer, a second active layer, a third undoped layer, a cap layer and contact layers are epitaxially grown on a semiconductor substrate in the stated order. A gate electrode is formed in a recess etched groove which formed in the center and reaches the cap layer through the contact layers. A drain electrode and a source electrode are formed on the contact layers and on both sides of the gate electrode.

    摘要翻译: 按照所述顺序在半导体衬底上外延生长缓冲层,第一未掺杂层,第一有源层和第二未掺杂层,第二有源层,第三未掺杂层,覆盖层和接触层。 栅电极形成在形成在中心并通过接触层到达盖层的凹陷蚀刻槽中。 漏电极和源电极形成在栅电极的接触层和两侧上。

    High power field effect transistor
    100.
    发明授权
    High power field effect transistor 失效
    大功率场效应晶体管

    公开(公告)号:US5382821A

    公开(公告)日:1995-01-17

    申请号:US988258

    申请日:1992-12-14

    申请人: Shigeru Nakajima

    发明人: Shigeru Nakajima

    CPC分类号: H01L29/42316

    摘要: There is disclosed an FET having a high drain breakdown voltage and a short gate length comprising an active layer 2 formed on a surface layer of a semiconductor substrate 1; a highly doped impurity source region 4 and highly doped impurity drain region 4 formed in the surface layer of the semiconductor substrate 1 to sandwich the active layer 2; an insulation film 5 formed on the highly doped impurity source region 4; a gate electrode 8 formed on the active layer 2 and the insulation film 5 while maintaining a constant distance 1.sub.GD from the highly doped impurity drain region 4; and a source electrode 6 and a drain electrode 7 formed on the highly doped impurity source region 4 and the highly doped impurity drain region 4, respectively.

    摘要翻译: 公开了一种具有高漏极击穿电压和短栅极长度的FET,其包括形成在半导体衬底1的表面层上的有源层2; 形成在半导体衬底1的表面层中以夹持有源层2的高掺杂杂质源区4和高掺杂杂质漏极区4; 形成在高掺杂杂质源区4上的绝缘膜5; 形成在有源层2和绝缘膜5上的栅电极8,同时保持与高掺杂杂质漏区4的距离1GD不变; 以及分别形成在高掺杂杂质源极区4和高掺杂杂质漏极区4上的源电极6和漏电极7。