Abstract:
A fuel cell system includes a fuel cell body to generate electrical energy using a reaction of hydrogen and oxygen; a reformer to generate a reformed gas containing hydrogen by reforming fuel and to supply the reformed gas to the fuel cell body; a fuel tank to store the fuel in a partially liquefied state and to supply the fuel to the reformer; a case to encase the fuel cell body and the reformer; and a refrigeration unit attached to the case to store ambient air of the fuel tank, the ambient air of the fuel tank being cooled by latent heat of vaporization of the fuel.
Abstract:
A perpendicular magnetic recording medium is provided, the perpendicular magnetic recording medium including: a substrate; a first soft magnetic underlayer formed on the substrate; a perpendicular anisotropic middle layer that is formed on the first soft magnetic underlayer and has perpendicular magnetic anisotropy; a second soft magnetic underlayer formed on the perpendicular anisotropic middle layer; and a perpendicular magnetic recording layer formed on the second soft magnetic underlayer.
Abstract:
A fuel cell reformer includes a main body having a first pipe with a second pipe inside the first pipe, a thermal source unit in the second pipe, a reforming reaction unit in a first region between the first pipe and the second pipe to generate a reforming gas containing hydrogen through a reforming reaction of a fuel, and a carbon monoxide reduction unit in a region other than the first region between the first pipe and the second pipe to reduce a concentration of carbon monoxide contained in the reforming gas. A thermal treatment unit in the main body supplies thermal energy to the reforming reaction unit and the carbon monoxide reduction unit at a time of initial driving of the reformer such that the supplied thermal energy corresponds to a unique operational temperature range in the reforming reaction unit, and to a unique operational temperature range in the carbon monoxide reduction unit.
Abstract:
In a semiconductor memory device including memory cells and a peripheral circuit unit, a memory cell has a first gate structure formed on a semiconductor substrate; a first impurity region of a first conductive type formed in the substrate on a first side of the gate structure; and a second impurity region formed in the substrate on a second side of the gate structure, the second impurity region including: a third impurity region of the first conductive type, a fourth impurity region of the first conductive type between the third impurity region and the second side of the gate structure, and a halo ion region of a second conductive type formed adjacent to the fourth impurity region.
Abstract:
Methods for fabricating a flash memory device which improves both charge retaining characteristics and characteristics of a gate insulating film are disclosed. The methods include the steps of respectively forming a tunneling oxide film and a peripheral oxide film on a cell and peripheral areas of a semiconductor substrate; forming a floating gate line on the tunneling oxide film; forming a first insulating film on a surface of the floating gate line; forming a second insulating film on an entire surface of the semiconductor substrate; forming a third insulating film on the second insulating film so that the third insulating film is thicker than the peripheral oxide film; removing the third insulating film and the second insulating film from the peripheral area by wet etching processes; removing the peripheral oxide film by a wet etching process; forming a gate insulating film on the surface of the semiconductor substrate in the peripheral area; depositing a conductive layer on the entire surface of the semiconductor substrate; selectively removing portions of the conductive layer, the third insulating film, the second insulating film, the first insulating film, and the floating gate line to form a control gate and a floating gate in the cell area, and a gate electrode of a thin film transistor in the peripheral area; and forming source/drain impurity areas within the surface of the semiconductor substrate at both sides of the control gate and floating gate and at both sides of the gate electrode.
Abstract:
Provided is a magnetic memory device. The magnetic memory device includes a first magnetization layer, a tunnel barrier disposed on the first magnetization layer, a second magnetization layer disposed on the tunnel barrier, and a spin current assisting layer disposed on at least a portion of a sidewall of the second magnetization layer.
Abstract:
A magnetic memory device includes a reference magnetic structure, a free magnetic structure, and a tunnel barrier pattern between the reference magnetic structure and the free magnetic structure. The reference magnetic structure includes a first pinned pattern, a second pinned pattern between the first pinned pattern and the tunnel barrier pattern, and an exchange coupling pattern between the first and the second pinned pattern. The second pinned pattern includes a first magnetic pattern adjacent the exchange coupling pattern, a second magnetic pattern adjacent the tunnel barrier pattern, a third magnetic pattern between the first and the second magnetic pattern, a first non-magnetic pattern between the first and the third magnetic pattern, and a second non-magnetic pattern between the second and the third magnetic pattern. The first non-magnetic pattern has a different crystal structure from the second non-magnetic pattern, and at least a portion of the third magnetic pattern is amorphous.
Abstract:
Magnetic memory devices may include a substrate, a circuit device on the substrate, a plurality of lower electrodes electrically connected to the circuit device, a magnetic tunnel junction (MTJ) structure commonly provided on the plurality of the lower electrodes, and a plurality of upper electrodes on the MTJ structure. The MTJ structure may include a plurality of magnetic material patterns and a plurality of insulation material patterns separating the magnetic material patterns from each other.
Abstract:
Provided are magnetoresistive elements, memory devices including the same, and an operation methods thereof. A magnetoresistive element may include a free layer, and the free layer may include a plurality of regions (layers) having different properties. The free layer may include a plurality of regions (layers) having different Curie temperatures. The Curie temperature of the free layer may change regionally or gradually away from the pinned layer. The free layer may include a first region having ferromagnetic characteristics at a first temperature and a second region having paramagnetic characteristics at the first temperature. The first region and the second region both may have ferromagnetic characteristics at a second temperature lower than the first temperature. The effective thickness of the free layer may change with temperature.
Abstract:
Magnetic memory devices include a magnetoresistive cell including a free layer having a variable magnetization direction and a pinned layer having a fixed magnetization direction, a bit line on the magnetoresistive cell and including a spin Hall effect material layer exhibiting a spin Hall effect and contacting the free layer; and a lower electrode under the magnetoresistive cell. A voltage is applied between the bit line and the lower electrode so that current passes through the magnetoresistive cell.