公开(公告)号：US07187721B1

公开(公告)日：2007-03-06

申请号：US09557164

申请日：2000-04-25

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H04L27/04

CPC分类号： H04L25/0282 ,  H04L25/028

摘要： Transition time of a data signal is controlled by applying different delays to the data signal and combining the delayed data signals. The transition time of the data output is determined by difference in delays applied to the data input and may be proportional to bit time of the bit clock. The data input may be applied directly to the delay elements or may be clocked by clock signals delayed by the delay elements. The delayed data is applied to parallel driver circuits. Supply voltage to the delay elements can be controlled to compensate for production and environmental variations. The supply voltage controller includes parallel delay elements of different delays and a phase comparator, the output of which controls the supply voltage applied to the delay elements.

摘要翻译： 通过对数据信号应用不同的延迟并组合延迟的数据信号来控制数据信号的转换时间。 数据输出的转换时间由施加到数据输入的延迟差确定，并且可以与位时钟的位时间成比例。 数据输入可以直接施加到延迟元件，或者可以由延迟元件延迟的时钟信号来计时。 延迟数据应用于并行驱动电路。 可以控制对延迟元件的供电电压以补偿生产和环境变化。 电源电压控制器包括具有不同延迟的并行延迟元件和相位比较器，其输出控制施加到延迟元件的电源电压。

公开(公告)号：US07187679B2

公开(公告)日：2007-03-06

申请号：US10246805

申请日：2002-09-18

申请人： William J. Dally ,  Philip P. Carvey ,  Larry R. Dennison ,  P. Allen King

发明人： William J. Dally ,  Philip P. Carvey ,  Larry R. Dennison ,  P. Allen King

IPC分类号： H04L12/56

CPC分类号： H04L49/251 ,  H04L45/06 ,  H04L45/10 ,  H04L49/10 ,  H04L49/101 ,  H04L49/30 ,  H04L49/50 ,  H04L49/505 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166 ,  H04L69/168

摘要： An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links. A virtual channel is enabled for possible assignment to an output fabric link upon receipt of an indication that an input buffer is available at the next fabric router of the path.

公开(公告)号：US07078979B2

公开(公告)日：2006-07-18

申请号：US11057078

申请日：2005-02-11

申请人： William J. Dally ,  Ramin Farjad-Rad ,  John W. Poulton ,  Thomas H. Greer, III ,  Hiok-Tiaq Ng ,  Teva J. Stone

发明人： William J. Dally ,  Ramin Farjad-Rad ,  John W. Poulton ,  Thomas H. Greer, III ,  Hiok-Tiaq Ng ,  Teva J. Stone

IPC分类号： H03B5/24 ,  H03L7/00 ,  H03L7/099

CPC分类号： H03L7/0805 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/083 ,  H03L7/091 ,  H03L7/0995 ,  H03L7/0998 ,  H03L7/20 ,  H03L7/23 ,  H03L7/24

摘要： An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

摘要翻译： 引起振荡器中的振荡信号朝耦合到振荡信号的输入信号的相位移相。 振荡器的谐振频率约等于输入信号频率的整数倍。 可以在脉冲发生器中产生输入信号以具有小于或等于振荡信号的输入脉冲持续时间的输入脉冲持续时间。 振荡器电路可以用作滤波器以滤除脉冲宽度变化或者从参考时钟滤波抖动。 振荡器电路也可以通过放大输入信号作为缓冲器。 可以通过将至少一个输入信号与至少一个振荡信号耦合来获得相位插值。

公开(公告)号：US07047391B2

公开(公告)日：2006-05-16

申请号：US11019979

申请日：2004-12-21

申请人： William J. Dally ,  Scott W. Rixner

发明人： William J. Dally ,  Scott W. Rixner

IPC分类号： G06F12/00

CPC分类号： G11C8/04 ,  G11C7/1006 ,  G11C11/408

摘要： A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

摘要翻译： 内存处理方法涉及实现内存状态驱动的访问。 根据示例实施例，处理在地址缓冲器处接收的地址，以相对于存储器中的活动位置访问存储器。 对应于存储器阵列中的活动位置的地址在不对应于活动位置的地址之前被处理。 将数据从存储器读取到读缓冲器，并以与地址缓冲器处的接收地址顺序相称的方式进行排序（例如，因此有助于以与地址缓冲器接收的顺序不同的顺序访问存储器，同时保持顺序 从读缓冲区）。

公开(公告)号：US07043562B2

公开(公告)日：2006-05-09

申请号：US10457718

申请日：2003-06-09

申请人： William J. Dally ,  William F. Mann ,  Philip P. Carvey

发明人： William J. Dally ,  William F. Mann ,  Philip P. Carvey

IPC分类号： G06F15/173

CPC分类号： G06F15/17337

摘要： Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backplane are connected in a single cycle which includes nodes on opposite sides of lower dimension tori. The cycles in adjacent backplanes hop different numbers of nodes.

公开(公告)号：US06976064B2

公开(公告)日：2005-12-13

申请号：US10456121

申请日：2003-06-06

申请人： Philip P. Carvey ,  William J. Dally ,  Larry R. Dennison

发明人： Philip P. Carvey ,  William J. Dally ,  Larry R. Dennison

IPC分类号： G06F15/173 ,  G06F15/80 ,  G06F15/177

CPC分类号： G06F15/17343 ,  G06F15/8023

摘要： A module connection assembly connects modules in a torus configuration that can be changed remotely. In particular, a single module can be added to or deleted from the configuration by remotely switching from conducting paths that provide end-around electrical paths to conducting paths that provide pass-through electrical paths. The assembly includes two backplanes, a first set of module connectors for electrically connecting modules to one of the backplanes, and a second set of module connectors for electrically connecting modules to the other backplane. The assembly further includes configuration controllers. Each configuration controller selects between end-around electrical paths that electrically connect multiple module connectors of the first set to each other, and pass-through electrical paths that electrically connect module connectors of the first set to module connectors of the second set. Each configuration controller operates as a remotely configurable switch that configures a topology formed by the backplanes and the module connectors. In particular, by adding a single module, the topology can be expanded incrementally.

摘要翻译： 模块连接组件连接可以远程更改的环面配置中的模块。 特别地，通过从提供终端电路径的导电路径远程切换到提供穿越电路径的导电路径，可以将单个模块添加到或从配置中删除。 该组件包括两个背板，用于将模块电连接到一个背板的第一组模块连接器，以及用于将模块电连接到另一背板的第二组模块连接器。 组件还包括配置控制器。 每个配置控制器在将第一组的多个模块连接器彼此电连接的末端电路之间进行选择，以及将第一组的模块连接器与第二组的模块连接器电连接的直通电路径。 每个配置控制器都可以作为远程配置开关，用于配置由背板和模块连接器形成的拓扑。 特别地，通过添加单个模块，可以逐渐扩展拓扑。

公开(公告)号：US06952431B1

公开(公告)日：2005-10-04

申请号：US09557640

申请日：2000-04-25

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H03K5/00 ,  H03K5/13 ,  H03L7/083 ,  H03L7/089 ,  H03L7/091 ,  H03L7/099 ,  H03L7/20 ,  H04J3/06 ,  H04L7/033

CPC分类号： H03L7/0995 ,  H03K5/133 ,  H03K2005/00026 ,  H03K2005/00228 ,  H03L7/083 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/20 ,  H04L7/0337

摘要： In a communications system, data is multiplexed onto a transmission medium at a transmitter and demultiplexed from the transmission medium at a receiver. The clock applied to the transmitter and receiver is a multiplying delay-locked loop in which a delay line provides a multiplied clock which is applied back to its input. A delay adjustment circuit including a proportional phase comparator of low offset adjusts delay in the delay line.

摘要翻译： 在通信系统中，数据被复用到发射机的传输介质上，并在接收机处从传输介质解复用。 施加到发射机和接收机的时钟是乘法延迟锁定环，其中延迟线提供被施加回其输入的相乘时钟。 包括低偏移的比例相位比较器的延迟调整电路调整延迟线中的延迟。

公开(公告)号：US06937073B2

公开(公告)日：2005-08-30

申请号：US09849920

申请日：2001-05-04

申请人： William J. Dally ,  Ramin Farjad-Rad ,  Teva J. Stone ,  Xiaoying Yu ,  John W. Poulton

发明人： William J. Dally ,  Ramin Farjad-Rad ,  Teva J. Stone ,  Xiaoying Yu ,  John W. Poulton

IPC分类号： H03L7/081 ,  H03L7/085 ,  H03L7/191 ,  H03B19/00

CPC分类号： H03D13/008 ,  H03L7/0812 ,  H03L7/085 ,  H03L7/0895 ,  H03L7/18 ,  H03L7/191

摘要： A phase comparison of timing signals is made by combinational circuitry which receives the timing signals and a window signal, the window signal identifying edges of the timing signals to be compared. The comparison may result in a charge pumped output which can be fed back to control the phase of one of the timing signals. The phase comparator and charge pump circuit can be included in a multiplier circuitry in which the phase of an input signal is directly compared to the phase of an edge of the multiplied signal.

摘要翻译： 定时信号的相位比较由接收定时信号和窗口信号的组合电路进行，窗口信号识别要比较的定时信号的边缘。 比较可能导致电荷泵浦输出，其可被反馈以控制其中一个定时信号的相位。 相位比较器和电荷泵电路可以包括在乘法器电路中，其中输入信号的相位与乘法信号的边沿的相位直接比较。

公开(公告)号：US06654381B2

公开(公告)日：2003-11-25

申请号：US09887960

申请日：2001-06-22

申请人： William J. Dally ,  Philip P. Carvey ,  Larry R. Dennison ,  P. Allen King

发明人： William J. Dally ,  Philip P. Carvey ,  Larry R. Dennison ,  P. Allen King

IPC分类号： H04L1228

CPC分类号： H04L49/602 ,  H04L45/00 ,  H04L45/06 ,  H04L45/10 ,  H04L45/40 ,  H04L45/60 ,  H04L47/10 ,  H04L47/122 ,  H04L47/30 ,  H04L49/10 ,  H04L49/101 ,  H04L49/15 ,  H04L49/1515 ,  H04L49/251 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/50 ,  H04L49/505 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166 ,  H04L69/168

摘要： A router routes data packets. The router includes input physical channels for incrementally receiving portions of the data packets, and output physical channels. The router further includes data buffers, coupled with the input and output physical channels, for storing the portions of the data packets. The router further includes control circuitry, coupled with the input and output physical channels and the data buffers, for generating virtual channel assignments that assign virtual channels to the data packets, and generating physical channel assignments that assign the output physical channels to the virtual channels. Each of the assignments is generated in response to queued arrival and credit events. The portions of the data packets are forwarded from the data buffers to the output physical channels according to the generate virtual and physical channel assignments.

摘要翻译： 路由器路由数据包。 路由器包括用于递增地接收数据分组的部分的输入物理信道，以及输出物理信道。 路由器还包括与输入和输出物理信道耦合的数据缓冲器，用于存储数据分组的部分。 路由器还包括与输入和输出物理信道以及数据缓冲器耦合的控制电路，用于生成将虚拟信道分配给数据分组的虚拟信道分配，以及生成将输出物理信道分配给虚拟信道的物理信道分配。 每个作业都是针对排队到达和信用事件而生成的。 根据生成的虚拟和物理信道分配，数据分组的部分从数据缓冲器转发到输出物理信道。

公开(公告)号：US06563831B1

公开(公告)日：2003-05-13

申请号：US09136235

申请日：1998-08-19

申请人： William J. Dally ,  Philip P. Carvey ,  Larry R. Dennison ,  P. Allen King

发明人： William J. Dally ,  Philip P. Carvey ,  Larry R. Dennison ,  P. Allen King

IPC分类号： H04L1228

CPC分类号： H04L49/602 ,  H04L45/00 ,  H04L45/06 ,  H04L45/10 ,  H04L45/40 ,  H04L45/60 ,  H04L47/10 ,  H04L47/122 ,  H04L47/30 ,  H04L49/10 ,  H04L49/101 ,  H04L49/15 ,  H04L49/1515 ,  H04L49/251 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/50 ,  H04L49/505 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166 ,  H04L69/168

摘要： An internet router is implemented as a network fabric of fabric routers and links. The internet router receives data packets from trunk lines or other internet links and analyzes header information in the data packets to route the data packets to output internet links. The line interface also analyzes the header to define a fabric path through the router fabric. The internet packets are broken into flits which are transferred through the router according to a wormhole routing protocol. Flits are stored in fabric routers at storage locations assigned to virtual channels corresponding to destination internet links. The virtual channels and links within the fabric define virtual networks in which congestion in one virtual network is substantially nonblocking to data flow through other virtual networks. Arbitration is performed at each fabric router to assign packets to virtual channels and to assign virtual channels to output fabric links. Data packets share access to multiple virtual channels, access being defined by dispersion code vectors. A virtual channel is enabled for possible assignment to an output fabric link upon receipt of an indication that an input buffer is available at the next fabric router of the path.

摘要翻译： 互联网路由器被实现为架构路由器和链路的网络结构。 互联网路由器从干线或其他互联网链路接收数据包，并分析数据包中的头信息，将数据包路由到输出互联网链路。 线路接口还分析头部以定义通过路由器结构的结构路径。 互联网数据包被分解成通过路由器根据虫洞路由协议传输的flits。 在分配给对应于目的地互联网链路的虚拟通道的存储位置处，将光纤存储在结构路由器中。 结构中的虚拟通道和链路定义虚拟网络，其中一个虚拟网络中的拥塞对于通过其他虚拟网络的数据流实质上是不阻塞的。 在每个结构路由器执行仲裁以将分组分配给虚拟通道，并将虚拟通道分配给输出结构链路。 数据分组共享对多个虚拟通道的访问，访问由分散码向量定义。 在接收到在路径的下一个结构路由器处输入缓冲器可用的指示时，启用虚拟通道以对输出结构链路进行可能的分配。