-
91.发明授权Multi-partition USB device that re-boots a PC to an alternate operating system for virus recovery 有权多分区USB设备，将PC重新启动到备用操作系统进行病毒恢复公开(公告)号：US07930531B2
公开(公告)日：2011-04-19
申请号：US11838192
申请日：2007-08-13
申请人： David Q. Chow , Charles C. Lee , Frank Yu , Tzu-Yih Chu , Ming-Shiang Shen
发明人： David Q. Chow , Charles C. Lee , Frank Yu , Tzu-Yih Chu , Ming-Shiang Shen
IPC分类号： G06F1/00
CPC分类号： G06F21/568 , G06F21/575 , G06F2221/2105 , G06F2221/2153
摘要： A multi-partition Universal Serial Bus (USB) device has a flash memory with multiple partitions of storage. Some partitions are for different operating systems and store OS images. Another partition has a control program while a user partition stores user data and user configuration information. The control program can test the multi-partition USB device and instruct the host computer BIOS to mount a partition from its flash memory as a drive of the host computer. The host computer can then be rebooted. The OS image from the flash memory is loaded into main memory during rebooting, and the host computer executes a new operating system using the new OS image. The user can press buttons on the multi-partition USB device to select which OS to load, and to begin rebooting. Virus removal programs in the alternate OS can help recover from a virus in the primary OS.
摘要翻译： 多分区通用串行总线（USB）设备具有具有多个存储分区的闪存。 一些分区用于不同的操作系统并存储操作系统映像。 另一个分区具有控制程序，而用户分区则存储用户数据和用户配置信息。 控制程序可以测试多分区USB设备，并指示主机BIOS将其闪存中的分区作为主机的驱动器安装。 然后可以重新启动主机。 重新启动时，闪存中的OS映像将加载到主内存中，主机使用新的操作系统映像执行新的操作系统。 用户可以按多分区USB设备上的按钮选择要加载的操作系统，并开始重新启动。 备用操作系统中的病毒清除程序可以帮助从主操作系统中的病毒恢复。
-
公开(公告)号：US07872871B2
公开(公告)日：2011-01-18
申请号：US11773830
申请日：2007-07-05
申请人： Siew S. Hiew , Jim C. Ni , Charles C. Lee , I-Kang Yu , Ming-Shiang Shen
发明人： Siew S. Hiew , Jim C. Ni , Charles C. Lee , I-Kang Yu , Ming-Shiang Shen
IPC分类号： H05K7/02
CPC分类号： G06F1/1632 , H01L24/97 , H01L2224/48091 , H01L2224/48227 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/12041 , H01L2924/14 , H01L2924/19041 , H05K1/117 , H05K3/0052 , H05K3/284 , H05K5/0278 , H05K2203/1316 , H01L2924/00014 , H01L2224/85
摘要： A low-profile Universal-Serial-Bus (USB) device includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips include, for example, a USB controller chip and a flash memory chip, or a single-chip (combined USB controller/flash memory) chip. Multiple flash IC chips are optionally stacked to increase storage capacity. The IC chip(s) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The low-profile USB device is optionally used as a modular insert that is mounted onto a metal case to provide a USB assembly having a plug shell similar to a standard USB male connector.
摘要翻译： 一个低调的通用串行总线（USB）设备包括一个PCBA，其中所有无源组件和未封装的IC芯片都连接到与金属触点相对的PCB的单面。 IC芯片例如包括USB控制器芯片和闪存芯片，或单芯片（组合的USB控制器/闪存）芯片。 可选择堆叠多个闪存IC芯片以增加存储容量。 IC芯片通过引线接合或其他芯片上（COB）芯片技术连接到PCB。 无源元件通过传统的表面贴装技术（SMT）技术连接起来。 然后在IC芯片和无源部件上形成模制外壳，使得该装置具有均匀的厚度。 低调USB设备可选地用作安装在金属外壳上的模块化插件，以提供具有类似于标准USB公连接器的插头外壳的USB组件。
-
公开(公告)号：US07850082B1
公开(公告)日：2010-12-14
申请号：US11932118
申请日：2007-10-31
IPC分类号： G06K7/08
CPC分类号： G06F13/385 , G06F2213/0042 , G06F2213/3804
摘要： An extended universal serial bus (USB) card reader device is described herein. In one embodiment, a card reader includes a first extended USB (EUSB) connector to be coupled to an external host system, multiple flash memory card sockets capable of receiving multiple flash memory cards inserted therein, multiple flash controllers coupled to the plurality of flash memory card sockets respectively. The card reader further includes a memory for storing executable code, a processor coupled to each of the flash controllers for executing the executable code to control each of the plurality of flash controllers in order to access the corresponding flash memory card inserted therein. The card reader further includes a second EUSB connector to be coupled to an external EUSB device using the extended USB protocols, which is one of an EUSB slave device and an EUSB hub device. Other methods and apparatuses are also described.
摘要翻译： 本文描述了扩展的通用串行总线（USB）读卡器设备。 在一个实施例中，读卡器包括要耦合到外部主机系统的第一扩展USB（EUSB）连接器，能够接收插入其中的多个闪存卡的多个闪存卡插槽，耦合到多个闪存的多个闪存控制器 卡插座。 读卡器还包括用于存储可执行代码的存储器，耦合到每个闪存控制器的处理器，用于执行可执行代码以控制多个闪存控制器中的每一个以便访问插入其中的相应闪存卡。 读卡器还包括使用作为EUSB从设备和EUSB集线器设备之一的扩展USB协议耦合到外部EUSB设备的第二EUSB连接器。 还描述了其它方法和装置。
-
94.发明授权Non-volatile memory device manufacturing process testing systems and methods thereof 失效非易失性存储器件制造工艺测试系统及其方法公开(公告)号：US07802155B2
公开(公告)日：2010-09-21
申请号：US12042316
申请日：2008-03-04
IPC分类号： G11C29/00
CPC分类号： G11C29/56 , G11C5/04 , G11C16/04 , G11C2029/0409
摘要： Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.
摘要翻译： 描述了制造和测试非易失性存储器（NVM）器件的系统和方法。 根据一个示例性实施例，在制造NVM模块期间的功能测试是通过包括计算机和经由外部总线耦合到计算机的NVM测试仪的系统进行的。 NVM测试仪包括多个槽。 每个插槽被配置为容纳待测试的相应的一个NVM模块。 NVM测试器被配置为包括输入/输出接口，具有相关联的RAM和ROM的微控制器，数据发生器，地址发生器，比较器，比较状态存储空间，测试结果指示器和NVM模块检测器。 数据发生器产生可重复的数据位序列作为测试向量。 已知的测试向量写入被测NVM模块的NVM。 然后将已知的测试向量与从NVM模块检索的数据进行比较。
-
95.发明授权Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages 失效闪存卡和具有集成电压转换器的控制器，用于连接到可在两个电源电压中任一个工作的总线公开(公告)号：US07483329B2
公开(公告)日：2009-01-27
申请号：US11625309
申请日：2007-01-20
申请人： Jianjun Luo , Chris Tsu , Charles C. Lee , Ming-Shiang Shen
发明人： Jianjun Luo , Chris Tsu , Charles C. Lee , Ming-Shiang Shen
IPC分类号： G11C5/14
摘要： A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.
摘要翻译： 可以将双电压安全数字（SD）卡插入到旧式主机或更新的主机中。 传统主机将高压（例如3.3伏特）驱动到SD总线的电源线上，而较新的主机则以1.8伏特的降低电压驱动电源线。 SD卡上的闪存和电压控制器芯片具有以降低的电压工作的控制器核心。 SD卡上的电压调节器或控制器芯片内的电源管理单元从双电压SD总线电源线产生1.8伏特的内部电源电压。 内部电源电压被施加到控制器核心和电压转换器，其从内部电源电压产生闪光电源电压。 闪存电源电压被施加到在更高电压下工作的SD卡上的闪存芯片。
-
96.发明授权Memory address management systems in a large capacity multi-level cell (MLC) based flash memory device 有权大容量多级单元（MLC）闪存设备中的内存地址管理系统公开(公告)号：US08015348B2
公开(公告)日：2011-09-06
申请号：US12980591
申请日：2010-12-29
IPC分类号： G06F12/08
CPC分类号： H05K1/182 , G06F12/00 , H01R13/447 , H05K1/181 , H05K5/0278 , H05K2201/10189 , H05K2201/10446 , H05K2203/1572
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译： 描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。 根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。 闪存被分为N组。 每个集合包括多个条目（即，块）。 对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。 只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。 在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。 与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。
-
97.发明申请公开(公告)号：US20080320209A1
公开(公告)日：2008-12-25
申请号：US12141879
申请日：2008-06-18
CPC分类号： G06F13/161 , G06F12/0246 , G06F2212/7201 , G06F2212/7203
摘要： High performance and endurance non-volatile memory (NVM) based storage systems are disclosed. According to one aspect of the present invention, a NVM based storage system comprises at least one intelligent NVM device. Each intelligent NVM device includes a control interface logic and NVM. Logical-to-physical address conversion is performed within the control interface logic, thereby eliminating the need of address conversion in a storage system level controller. In another aspect, a volatile memory buffer together with corresponding volatile memory controller and phase-locked loop circuit is included in a NVM based storage system. The volatile memory buffer is partitioned to two parts: a command queue; and one or more page buffers. The command queue is configured to hold received data transfer commands by the storage protocol interface bridge, while the page buffers are configured to hold data to be transmitted between the host computer and the at least one NVM device.
摘要翻译： 公开了基于高性能和耐久性非易失性存储器（NVM）的存储系统。 根据本发明的一个方面，一种基于NVM的存储系统包括至少一个智能NVM设备。 每个智能NVM设备都包括一个控制接口逻辑和NVM。 在控制接口逻辑中执行逻辑到物理地址转换，从而消除了存储系统级控制器中地址转换的需要。 在另一方面，在基于NVM的存储系统中包括易失性存储器缓冲器以及相应的易失性存储器控制器和锁相环电路。 易失性存储缓冲区分为两部分：命令队列; 和一个或多个页面缓冲区。 命令队列被配置为通过存储协议接口桥保存接收到的数据传输命令，而页缓冲器被配置为保存要在主计算机和至少一个NVM设备之间传输的数据。
-
98.发明申请Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof 失效非易失性存储器件制造工艺测试系统及其方法公开(公告)号：US20080201622A1
公开(公告)日：2008-08-21
申请号：US12042316
申请日：2008-03-04
CPC分类号： G11C29/56 , G11C5/04 , G11C16/04 , G11C2029/0409
摘要： Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module.
摘要翻译： 描述了制造和测试非易失性存储器（NVM）器件的系统和方法。 根据一个示例性实施例，在制造NVM模块期间的功能测试是通过包括计算机和经由外部总线耦合到计算机的NVM测试仪的系统进行的。 NVM测试仪包括多个槽。 每个插槽被配置为容纳待测试的相应的一个NVM模块。 NVM测试器被配置为包括输入/输出接口，具有相关联的RAM和ROM的微控制器，数据发生器，地址发生器，比较器，比较状态存储空间，测试结果指示器和NVM模块检测器。 数据发生器产生可重复的数据位序列作为测试向量。 已知的测试向量写入被测NVM模块的NVM。 然后将已知的测试向量与从NVM模块检索的数据进行比较。
-
公开(公告)号：US20080147968A1
公开(公告)日：2008-06-19
申请号：US12017249
申请日：2008-01-21
IPC分类号： G06F12/02
CPC分类号： G06F11/1068 , G11C5/04
摘要： High performance flash memory devices (FMD) are described. According to one exemplary embodiment of the invention, a high performance FMD includes an I/O interface, a FMD controller, and at least one non-volatile memory module along with corresponding at least one channel controller. The I/O interface is configured to connect the high performance FMD to a host computing device The FMD contoller is configured to control data transfer (e.g., data reading, data writing/programming, and data erasing) operations between the host computing device and the non-volatile memory module. The at least one non-volatile memory module, comprising one or more non-volatile memory chips, is configured as a secondary storage for the host computing device. The at least one channel controller is configured to ensure proper and efficient data transfer between a set of data buffers located in the FMD controller and the at least one non-volatile memory module.
摘要翻译： 描述了高性能闪存设备（FMD）。 根据本发明的一个示例性实施例，高性能FMD包括I / O接口，FMD控制器以及至少一个非易失性存储器模块以及对应的至少一个通道控制器。 I / O接口被配置为将高性能FMD连接到主机计算设备FMD控制器被配置为控制主计算设备和主计算设备之间的数据传输（例如，数据读取，数据写入/编程和数据擦除）操作 非易失性内存模块。 包括一个或多个非易失性存储器芯片的至少一个非易失性存储器模块被配置为主计算设备的辅助存储器。 至少一个通道控制器被配置为确保位于FMD控制器和至少一个非易失性存储器模块中的一组数据缓冲器之间的适当和有效的数据传输。
-
100.发明授权公开(公告)号：US08078794B2
公开(公告)日：2011-12-13
申请号：US11926743
申请日：2007-10-29
IPC分类号： G06F13/00
CPC分类号： G06F12/1416 , G06F3/0613 , G06F3/0643 , G06F3/0688 , G06F12/0246 , G06F12/0866 , G06F21/32 , G06F21/78 , G06F2212/2022 , G06F2212/7202 , G07C9/00087 , G11C2211/5641
摘要： Hybrid solid state drives (SSD) using a combination of single-level cell (SLC) and multi-level cell (MLC) flash memory arrays are described. According to one aspect of the present invention, a hybrid SSD is built using a combination SLC and MLC flash memory arrays. The SSD also includes a micro-controller to control and coordinate data transfer from a host computing device to either the SLC flash memory array of the MLC flash memory array. A memory selection indicator is determined by triaging data file based on one or more criteria, which include, but is not limited to, storing system files and user directories in the SLC flash memory array and storing user files in the MLC flash memory array; or storing more frequent access files in the SLC flash memory array, while less frequent accessed files in the MLC flash memory array.
摘要翻译： 描述了使用单级单元（SLC）和多级单元（MLC）闪存阵列的组合的混合固态驱动器（SSD）。 根据本发明的一个方面，使用组合SLC和MLC闪存阵列构建混合SSD。 SSD还包括一个微控制器，用于控制和协调从主机计算设备到MLC闪存阵列的SLC闪存阵列的数据传输。 存储器选择指示符通过基于一个或多个标准进行分类数据文件来确定，所述标准包括但不限于将系统文件和用户目录存储在SLC闪速存储器阵列中并将用户文件存储在MLC闪速存储器阵列中; 或将更频繁的访问文件存储在SLC闪存阵列中，而在MLC闪存阵列中访问的文件较少。
-
-
-
-
-
-
-
-
-
搜索结果
190 条记录 (耗时 0.034 秒)