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    ON-DEMAND IP INITIALIZATION WITHIN POWER STATES
    92.
    发明申请
    ON-DEMAND IP INITIALIZATION WITHIN POWER STATES 有权

    公开(公告)号：US20230031388A1

    公开(公告)日：2023-02-02

    申请号：US17390429

    申请日：2021-07-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Benjamin Tsien ,  Indrani Paul ,  Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Christopher T. Weaver

    IPC: G06F1/3203

    Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

    Power management for heterogeneous computing systems
    95.
    发明授权
    Power management for heterogeneous computing systems 有权

    公开(公告)号：US10168762B2

    公开(公告)日：2019-01-01

    申请号：US14857574

    申请日：2015-09-17

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Can Hankendi ,  Manish Arora ,  Indrani Paul

    IPC: G06F1/32

    Abstract: A computing system includes a set of computing resources and a datastore to store information representing a corresponding idle power consumption metric and a corresponding peak power consumption metric for each computing resource of the set. The computing system further includes a controller coupled to the set of computing resources and the datastore. The controller is to configure the set of computing resources to meet a power budget constraint for the set based on the corresponding idle power consumption metric and the corresponding peak power consumption metric for each computing resource of the set.

    POWER EFFICIENCY OPTIMIZATION IN THROUGHPUT-BASED WORKLOADS
    96.
    发明申请
    POWER EFFICIENCY OPTIMIZATION IN THROUGHPUT-BASED WORKLOADS 审中-公开

    公开(公告)号：US20180364782A1

    公开(公告)日：2018-12-20

    申请号：US16011476

    申请日：2018-06-18

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Leonardo De Paula Rosa Piga ,  Samuel Naffziger ,  Ivan Matosevic ,  Indrani Paul

    IPC: G06F1/32

    Abstract: A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.

    Power management of instruction processors in a system-on-a-chip
    97.
    发明授权
    Power management of instruction processors in a system-on-a-chip 有权

    公开(公告)号：US10133574B2

    公开(公告)日：2018-11-20

    申请号：US15181837

    申请日：2016-06-14

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Akanksha Jain ,  Wei Huang ,  Indrani Paul

    IPC: G06F9/30 ,  G06F1/32

    Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

    System and method for determining concurrency factors for dispatch size of parallel processor kernels
    98.
    发明授权
    System and method for determining concurrency factors for dispatch size of parallel processor kernels 有权

    公开(公告)号：US09965343B2

    公开(公告)日：2018-05-08

    申请号：US14710879

    申请日：2015-05-13

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Rathijit Sen ,  Indrani Paul ,  Wei Huang

    IPC: G06F9/54 ,  G06F9/445

    CPC classification number: G06F9/545 ,  G06F9/44505 ,  Y02D10/43

    Abstract: Disclosed is a method of determining concurrency factors for an application running on a parallel processor. Also disclosed is a system for implementing the method. In an embodiment, the method includes running at least a portion of the kernel as sequences of mini-kernels, each mini-kernel including a number of concurrently executing workgroups. The number of concurrently executing workgroups is defined as a concurrency factor of the mini-kernel. A performance measure is determined for each sequence of mini-kernels. From the sequences, a particular sequence is chosen that achieves a desired performance of the kernel, based on the performance measures. The kernel is executed with the particular sequence.

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