公开(公告)号：US07473623B2

公开(公告)日：2009-01-06

申请号：US11428022

申请日：2006-06-30

申请人： Jian Chen ,  Mark W. Michael

发明人： Jian Chen ,  Mark W. Michael

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823418 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.

摘要翻译： 一种方法包括在第一区域中的半导体层上形成多个功能特征。 相邻于功能特征的非功能特征形成在邻近设置在区域周边的功能特征中的至少一个功能特征。 在功能特征和非功能特征的至少一部分上形成应力诱导层。 一种器件包括半导体层，第一伪栅电极和应力诱导层。 多个晶体管栅电极形成在半导体层的上方。 多个至少包括第一端栅极电极，第二端栅极电极和至少一个内部栅极电极。 第一虚拟栅电极设置在第一端栅电极附近。 应力感应层设置在多个晶体管栅极电极和第一虚拟栅电极的至少一部分上。

公开(公告)号：US06867130B1

公开(公告)日：2005-03-15

申请号：US10445936

申请日：2003-05-28

申请人： Olov B. Karlsson ,  Simon S. Chan ,  William G. En ,  Mark W. Michael

发明人： Olov B. Karlsson ,  Simon S. Chan ,  William G. En ,  Mark W. Michael

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/44 ,  H01L21/4763 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66507 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/42376 ,  H01L29/6659 ,  H01L29/7833

摘要： Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.

摘要翻译： 通过在栅极电极和源极/漏极区域上形成薄金属硅化物层，然后选择性地使栅电极重新硅化，来制造在源极/漏极区域中显示出降低的栅极电阻和减少的硅化物尖峰的半导体器件。 实施例包括在多晶硅栅极电极和源极/漏极区域上形成薄金属硅化物层，通过高密度等离子体沉积沉积介电间隙填充层，回蚀刻以选择性地暴露硅化多晶硅栅电极并使多晶硅栅电极重新硅化 增加其上的金属硅化物层的厚度。 实施例还包括重新硅化多晶硅栅电极，其包括形成蘑菇状金属硅化物层的上侧表面的一部分。

公开(公告)号：US06764917B1

公开(公告)日：2004-07-20

申请号：US10023350

申请日：2001-12-20

申请人： Darin A. Chan ,  William G. En ,  John G. Pellerin ,  Mark W. Michael

发明人： Darin A. Chan ,  William G. En ,  John G. Pellerin ,  Mark W. Michael

IPC分类号： H01L2176

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

摘要翻译： 制造半导体器件的方法包括在绝缘层上提供硅半导体层，并部分地去除硅层的第一部分。 硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，硅层的第一和第二部分最初可以具有相同的厚度。 还公开了一种半导体器件。

公开(公告)号：US06261885B1

公开(公告)日：2001-07-17

申请号：US09497789

申请日：2000-02-03

申请人： Jon D. Cheek ,  Daniel Kadosh ,  Mark W. Michael

发明人： Jon D. Cheek ,  Daniel Kadosh ,  Mark W. Michael

IPC分类号： H01L218238

CPC分类号： H01L21/82345

摘要： A method for fabricating an integrated circuit is presented wherein a first polysilicon layer dielectrically spaced above a semiconductor substrate is provided. The semiconductor substrate contains a first active region and a second active region. A first dopant is selectively introduced into the portion of the first polysilicon layer above the second active region. A second polysilicon layer may then be formed upon the first polysilicon layer and above the first active region and the second active region. A second dopant may be selectively introduced into a portion of the second polysilicon layer above the first active region. The portion of the second polysilicon layer above the first active region and the portion of the first polysilicon layer above the first active region may be patterned to form a first gate structure within the first active region. The portion of the second polysilicon layer above the second active region and the portion of the first polysilicon layer above the second active region may be patterned to form a second gate structure within the second active region.

摘要翻译： 提出了一种用于制造集成电路的方法，其中提供介于半导体衬底之上的第一多晶硅层。 半导体衬底包含第一有源区和第二有源区。 第一掺杂剂被选择性地引入第二有源区上方的第一多晶硅层的部分。 然后可以在第一多晶硅层上并且在第一有源区和第二有源区上方形成第二多晶硅层。 可以将第二掺杂剂选择性地引入第一有源区上方的第二多晶硅层的一部分。 在第一有源区上方的第二多晶硅层的部分和第一有源区上方的第一多晶硅层的部分可以被图案化以在第一有源区内形成第一栅极结构。 在第二有源区上方的第二多晶硅层的部分和第二有源区上方的第一多晶硅层的部分可以被图案化以在第二有源区内形成第二栅极结构。

公开(公告)号：US07793240B2

公开(公告)日：2010-09-07

申请号：US11537390

申请日：2006-09-29

申请人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

发明人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

摘要翻译： 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US07391226B2

公开(公告)日：2008-06-24

申请号：US11421217

申请日：2006-05-31

申请人： Mark W. Michael ,  Raymond G. Stephany

发明人： Mark W. Michael ,  Raymond G. Stephany

IPC分类号： G01R27/08 ,  G01R31/26 ,  H01L29/10

CPC分类号： G01R31/2884

摘要： The present invention is directed to a contact resistance test structure and methods of using same. In one illustrative embodiment, the method includes forming a test structure comprised of two gate electrode structures, forming a plurality of conductive contacts to a doped region between the two gate electrode structures, forcing a current through the test structure and determining a resistance of at least one of the conductive contacts based upon, in part, the forced current.

摘要翻译： 本发明涉及一种接触电阻测试结构及其使用方法。 在一个说明性实施例中，该方法包括形成由两个栅极电极结构组成的测试结构，在两个栅电极结构之间的掺杂区域上形成多个导电触点，迫使通过测试结构的电流和至少确定电阻 导电触点之一部分地基于强制电流。

公开(公告)号：US20070298524A1

公开(公告)日：2007-12-27

申请号：US11425913

申请日：2006-06-22

申请人： DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

发明人： DAVID D. WU ,  Mark W. Michael ,  Akif Sultan ,  Jingrong Zhou

IPC分类号： H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  G03F7/70658 ,  H01L22/12

摘要： The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

摘要翻译： 本发明涉及量化由各种特征的制造引起的角舍入引起的变化的方法和用于测试相同结构的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个测试结构，每个测试结构具有相对于多个测试结构中的另一个变化的至少一个物理尺寸，至少一些测试结构 表现出至少一定程度的制造引起的角落四舍五入，形成至少一个参考测试结构，对多个测试结构和参考测试结构进行至少一次电测试，从而产生电测试结果，并分析测试结果 以确定制造性角落四舍五入对多个测试结构的性能的影响。

公开(公告)号：US20070296444A1

公开(公告)日：2007-12-27

申请号：US11426723

申请日：2006-06-27

申请人： Jianhong Zhu ,  David D. Wu ,  Mark W. Michael

发明人： Jianhong Zhu ,  David D. Wu ,  Mark W. Michael

IPC分类号： G01R31/02 ,  G01R31/26

CPC分类号： G01R31/2884 ,  G01R31/2648

摘要： A test structure includes first and second combs, at least a first pair of base nodes, and a second pair of finger nodes. The first comb includes a first base and a first plurality of fingers extending from the first base. The second comb includes a second base and a second plurality of fingers extending from the second base. At least a portion of the first and second pluralities of fingers are interleaved. The first pair of base nodes extend from the first base. The second pair of finger nodes extend from a first finger of the first plurality of fingers.

摘要翻译： 测试结构包括第一和第二梳，至少第一对基本节点和第二对​​手指节点。 第一梳子包括从第一基部延伸的第一基部和第一多个指状物。 第二梳子包括从第二基部延伸的第二基部和第二多个指状物。 第一和第二多个手指的至少一部分交错。 第一对基本节点从第一个基地延伸。 所述第二对手指节点从所述第一多个手指的第一手指延伸。

公开(公告)号：US06841832B1

公开(公告)日：2005-01-11

申请号：US10021497

申请日：2001-12-19

申请人： William G. En ,  Mark W. Michael ,  Hai Hong Wang ,  Simon Siu-Sing Chan

发明人： William G. En ,  Mark W. Michael ,  Hai Hong Wang ,  Simon Siu-Sing Chan

IPC分类号： H01L21/66 ,  H01L21/8234 ,  H01L23/544 ,  H01L27/08 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L22/34 ,  H01L21/823437 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

公开(公告)号：US06713357B1

公开(公告)日：2004-03-30

申请号：US10023348

申请日：2001-12-20

申请人： Hai Hong Wang ,  Mark W. Michael ,  Wen-Jie Qi ,  William G. En ,  John G. Pellerin

发明人： Hai Hong Wang ,  Mark W. Michael ,  Wen-Jie Qi ,  William G. En ,  John G. Pellerin

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L21/76834 ,  H01L23/3171 ,  H01L29/4983 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.

摘要翻译： 本发明涉及制造具有减小的寄生电容的MOS晶体管的方法。 本发明基于通过使用具有优化的横截面形状的侧壁间隔件与上覆绝缘体（例如CMOS）和IC器件的制造中的MOS晶体管的寄生电容相结合的方式， 层由低k电介质材料组成。