公开(公告)号：US06577160B2

公开(公告)日：2003-06-10

申请号：US10170026

申请日：2002-06-10

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联。 本地导体与每个区域相关联。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US06300794B1

公开(公告)日：2001-10-09

申请号：US09488025

申请日：2000-01-20

申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

IPC分类号： H01L2500

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

公开(公告)号：US06225823B1

公开(公告)日：2001-05-01

申请号：US09535635

申请日：2000-03-24

申请人： Christopher F. Lane ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Edward Jefferson

发明人： Christopher F. Lane ,  Srinivas T. Reddy ,  Andy L. Lee ,  David Edward Jefferson

IPC分类号： H03K19177

CPC分类号： H03K19/17744

摘要： A programmable logic device has a plurality of conductors extending around its periphery for use in providing at least some of the signals needed for control of input/output (“I/O”) pins which are also disposed around the periphery of the device. These control signals may include clock signals, output enable signals, clock enable signals, clear signals, or the like. The conductors that thus extend around the periphery are segmented into plural segments that can either be used independently of one another or programmably stitched together and therefore used together.

摘要翻译： 可编程逻辑器件具有围绕其周边延伸的多个导体，用于提供控制输入/输出（“I / O”）引脚所需的至少一些信号，该引脚也设置在器件周围。 这些控制信号可以包括时钟信号，输出使能信号，时钟使能信号，清除信号等。 因此，围绕周边延伸的导体被分割成多个段，其可以彼此独立地使用或可编程地缝合在一起，因此一起使用。

公开(公告)号：US06202185B1

公开(公告)日：2001-03-13

申请号：US09169177

申请日：1998-10-08

申请人： Andy L. Lee

发明人： Andy L. Lee

IPC分类号： G01R3128

CPC分类号： G01R31/318558

摘要： Scan testing of logic circuitry is facilitated by providing register circuits, each having an input gate configured to selectively pass a data s signal applied to that register, a master stage configured to store a data signal passed by the input gate of that register, an interstage gate configured to selectively pass a data signal stored by the master stage of that register, and a slave stage configured to store a data signal passed by the interstage gate of that register. Inter-register gates are operatively arranged to selectively pass a data signal stored by the master stage of an associated respective first one of the registers to the master stage of an associated respective second one of the registers for storage by the master stage of that second one of the registers. During normal operation, circuitry is configured to alternately enable the input gates and the interstage gates, and to disable the inter-register gates. During a scan mode, circuitry is configured to disable the input gates and the interstage gates, and to alternately enable alternate ones of the inter-register gates.

摘要翻译： 逻辑电路的扫描测试通过提供寄存器电路来实现，每个寄存器电路具有被配置为选择性地传递施加到该寄存器的数据信号的输入门，配置成存储由该寄存器的输入门通过的数据信号的主级，级间 被配置为选择性地传递由该寄存器的主级存储的数据信号，以及被配置为存储由该寄存器的级间门通过的数据信号的从级。 同步寄存器门被可操作地布置成选择性地将由相关联的相应的第一个寄存器的主级存储的数据信号传送到相关联的相应的第二寄存器的主级，以由第二个的主级存储 的寄存器。 在正常操作期间，电路被配置为交替地启用输入门和级间门，并且禁用寄存器间门。 在扫描模式期间，电路被配置为禁用输入门和级间门，并且交替地使得寄存器间的门中的替代地址。

公开(公告)号：US6107824A

公开(公告)日：2000-08-22

申请号：US86302

申请日：1998-05-28

申请人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

发明人： Srinivas T. Reddy ,  Ketan Zaveri ,  Christopher F. Lane ,  Andy L. Lee ,  Cameron R. McClintock ,  Bruce B. Pedersen ,  Manuel Mejia ,  Richard G. Cliff

IPC分类号： H03K19/177 ,  G06F7/38 ,  H01L25/00

CPC分类号： H03K19/17736 ,  H03K19/17792

摘要： Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

公开(公告)号：US08788550B1

公开(公告)日：2014-07-22

申请号：US12484010

申请日：2009-06-12

申请人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

发明人： Ketan Padalia ,  David Cashman ,  David Lewis ,  Andy L. Lee ,  Jay Schleicher ,  Jinyong Yuan ,  Henry Kim

IPC分类号： G06F7/38

CPC分类号： G06F7/575 ,  H03K19/177 ,  H03K19/17728

摘要： A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB includes a logic element (LE) configurable to arithmetically combine a plurality of binary input signals in a plurality of stages. The LE comprises look-up table (LUT) logic having K inputs (a “K-LUT”). The K-LUT is configured to input the binary input signals at respective inputs of the K-LUT logic cell and to provide, at a plurality of outputs of the K-LUT logic cell, respective binary result signals indicative of at least two of the plurality of stages of the arithmetic combination of binary input signals. An input line network includes a network of input lines, the input lines configurable to receive input signals from the PLD routing architecture that represent the binary input signals and to provide the input signals to the K-LUT. An output line network includes a network of output lines, the output lines configured to receive, from the K-LUT, output signals that represent the binary result signals and to provide the output signals to the PLD routing architecture. The described LUT's can perform arithmetic efficiently, as well as non-arithmetic functions.

摘要翻译： 可编程逻辑器件（PLD）包括通过PLD路由架构连接的多个逻辑阵列块（LAB）。 至少一个LAB包括可配置为在多个级中算术组合多个二进制输入信号的逻辑元件（LE）。 LE包括具有K个输入（“K-LUT”）的查找表（LUT）逻辑。 K-LUT被配置为在K-LUT逻辑单元的相应输入处输入二进制输入信号，并且在K-LUT逻辑单元的多个输出处提供指示至少两个 二进制输入信号的算术组合的多级。 输入线网络包括输入线路网络，输入线路可配置为从PLD路由架构接收代表二进制输入信号的输入信号，并将输入信号提供给K-LUT。 输出线网络包括输出线网络，输出线路被配置为从K-LUT接收表示二进制结果信号的输出信号，并向PLD路由架构提供输出信号。 所描述的LUT可以有效地执行算术，以及非算术函数。

公开(公告)号：US08711614B1

公开(公告)日：2014-04-29

申请号：US13052374

申请日：2011-03-21

申请人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

发明人： Andy L. Lee ,  Irfan Rahim ,  Lu Zhou ,  Madhuri Mailavaram ,  Srinivas Perisetty

IPC分类号： G11C11/34

CPC分类号： G11C8/10

摘要： Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.

摘要翻译： 提供了存储器元件，当受到诸如高能量原子粒子撞击的辐射攻击时，其表现出对软错误失调事件的抗扰性。 存储器元件可以各自具有形成双稳态元件和一对地址晶体管的四个反相器状晶体管对。 晶体管中可能存在四个节点，每个节点与四个逆变器状晶体管对中的相应一个相关联。 可以存在两个控制晶体管，每个控制晶体管耦合在逆变器状晶体管对的相应一个中的晶体管之间。 在数据写入操作期间，可以关闭两个控制晶体管，以暂时将四个反相器状晶体管对中的两个中的晶体管去耦。

公开(公告)号：US08644100B2

公开(公告)日：2014-02-04

申请号：US13277871

申请日：2011-10-20

申请人： Philip Pan ,  Andy L. Lee ,  Lu Zhou ,  Aniket Kadkol

发明人： Philip Pan ,  Andy L. Lee ,  Lu Zhou ,  Aniket Kadkol

IPC分类号： G11C7/00

CPC分类号： G11C11/418 ,  G11C7/00 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4094 ,  G11C11/413 ,  G11C11/419 ,  G11C29/12 ,  G11C2029/0409 ,  G11C2029/1204 ,  G11C2029/2602

摘要： An integrated circuit having a logic element that includes an array of storage elements convertibly functioning as either a configuration random access memory (CRAM) or a static random access memory (SRAM) is provided. The logic element includes first and second pairs of data paths having dedicated multiplexers. In one embodiment, the first and second pairs of data paths are multiplexed into bit lines of a row of the array. The logic element also includes a data path control block generating control signals for each of the dedicated multiplexers. The control signals determine whether the storage elements function as a CRAM or a SRAM. A method for selectively configuring a memory array between a CRAM mode and SRAM mode are provided.

摘要翻译： 提供一种集成电路，其具有包括可转换地用作配置随机存取存储器（CRAM）或静态随机存取存储器（SRAM））的存储元件阵列的逻辑元件。 逻辑元件包括具有专用复用器的第一和第二对数据路径。 在一个实施例中，第一和第二对数据路径被复用到阵列行的位线。 逻辑元件还包括数据路径控制块，其产生用于每个专用多路复用器的控制信号。 控制信号确定存储元件是否用作CRAM或SRAM。 提供了一种用于在CRAM模式和SRAM模式之间选择性地配置存储器阵列的方法。

公开(公告)号：US08198914B2

公开(公告)日：2012-06-12

申请号：US13098450

申请日：2011-04-30

申请人： Andy L. Lee ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Richard G. Cliff ,  Cameron R. McClintock ,  Srinivas T. Reddy ,  David Lewis

发明人： Andy L. Lee ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Richard G. Cliff ,  Cameron R. McClintock ,  Srinivas T. Reddy ,  David Lewis

IPC分类号： H01L25/00

CPC分类号： H03K19/17784 ,  H03K19/17788 ,  H03K19/17792

摘要： A programmable logic device (PLD) includes at least two regions. Each region includes electrical circuitry that has a set of transistors. Each of the two regions has a corresponding fixed transistor threshold voltage, a corresponding fixed transistor body bias, and a corresponding fixed supply voltage.

摘要翻译： 可编程逻辑器件（PLD）至少包括两个区域。 每个区域包括具有一组晶体管的电路。 两个区域中的每一个具有对应的固定晶体管阈值电压，对应的固定晶体管体偏置和相应的固定电源电压。

公开(公告)号：US08130574B2

公开(公告)日：2012-03-06

申请号：US13024666

申请日：2011-02-10

申请人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

发明人： Ninh D. Ngo ,  Andy L. Lee ,  Kerry Veenstra

IPC分类号： G11C29/00

CPC分类号： H03K19/17764 ,  G06F11/1004

摘要： Error detection circuitry is provided on a programmable logic resource. Programmable logic resource configuration data is loaded into a cyclic redundancy check (CRC) module where a checksum calculation may be performed. In one embodiment, the checksum may be compared to an expected value, which is a precomputed checksum on data prior to being programmed into or while data is being programmed into a programmable logic resource. In another embodiment, the expected value may be included in the checksum calculation. An output indicating whether an error is detected may be generated depending on the relationship between the checksum and the expected value, or on the value of the checksum. This output may be sent to an output pin that is accessible by user logic.

摘要翻译： 在可编程逻辑资源上提供错误检测电路。 可编程逻辑资源配置数据被加载到可以执行校验和计算的循环冗余校验（CRC）模块中。 在一个实施例中，校验和可以与预期值进行比较，期望值是在被编程到数据被编程到可编程逻辑资源之前或数据被编程到数据之前的预计算校验和。 在另一个实施例中，期望值可以包括在校验和计算中。 可以根据校验和和期望值之间的关系或校验和的值来生成指示是否检测到错误的输出。 该输出可以被发送到用户逻辑可访问的输出引脚。