公开(公告)号：US08472258B2

公开(公告)日：2013-06-25

申请号：US13269425

申请日：2011-10-07

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20120196411A1

公开(公告)日：2012-08-02

申请号：US13363268

申请日：2012-01-31

申请人： Ryuta TSUCHIYA ,  Shinichiro Kimura

发明人： Ryuta TSUCHIYA ,  Shinichiro Kimura

IPC分类号： H01L21/336

CPC分类号： H01L27/12 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1207

摘要： A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

摘要翻译： 一种器件及其制造方法，其中，器件包括单晶半导体衬底和通过薄的掩埋绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的SOI衬底 以相同的步骤形成SOI型MISFET和体型MISFET的良好扩散层区域，漏极区域，栅极绝缘膜和栅极电极。 本体型MISFET和SOI型MISFET形成在同一衬底上，从而通过制造SOI型MISFET和体型MISFET的制造步骤，可以减少电路板面积并简化工艺。

公开(公告)号：US08143668B2

公开(公告)日：2012-03-27

申请号：US12481551

申请日：2009-06-09

申请人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823828 ,  H01L21/823864

摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。

公开(公告)号：US20120061774A1

公开(公告)日：2012-03-15

申请号：US13299471

申请日：2011-11-18

申请人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

发明人： Yusuke Morita ,  Ryuta Tsuchiya ,  Takashi Ishigaki ,  Nobuyuki Sugii ,  Shinichiro Kimura

IPC分类号： H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823828 ,  H01L21/823864

摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.

摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。

公开(公告)号：US20120026798A1

公开(公告)日：2012-02-02

申请号：US13269425

申请日：2011-10-07

申请人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh HISAMOTO ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C16/10

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US20120018807A1

公开(公告)日：2012-01-26

申请号：US13145108

申请日：2010-01-18

申请人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

发明人： Ryuta Tsuchiya ,  Nobuyuki Sugii ,  Yusuke Morita ,  Hiroyuki Yoshimoto ,  Takashi Ishigaki ,  Shinichiro Kimura

IPC分类号： H01L27/12 ,  B82Y99/00

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/78648

摘要： In an SOI-MISFET that operates with low power consumption at a high speed, an element area is reduced. While a diffusion layer region of an N-conductivity type MISFET region of the SOI type MISFET and a diffusion layer region of a P-conductivity type MISFET region of the SOI type MISFET are formed as a common region, well diffusion layers that apply substrate potentials to the N-conductivity type MISFET region and the P-conductivity type MISFET region are separated from each other by an STI layer. The diffusion layer regions that are located in the N- and P-conductivity type MISFET regions) and serve as an output portion of a CMISFET are formed as a common region and directly connected by silicified metal so that the element area is reduced.

摘要翻译： 在以高功率低功耗工作的SOI-MISFET中，元件面积减小。 虽然SOI型MISFET的N导电型MISFET区域的扩散层区域和SOI型MISFET的P导电型MISFET区域的扩散层区域形成为公共区域，但是施加衬底电位的阱扩散层 通过STI层将N导电型MISFET区域和P导电型MISFET区域相互分离。 位于N和P导电型MISFET区域中的扩散层区域）作为CMISFET的输出部分形成为公共区域，并通过硅化金属直接连接，使元件面积减小。

公开(公告)号：US08076709B2

公开(公告)日：2011-12-13

申请号：US12873679

申请日：2010-09-01

申请人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

发明人： Tetsuya Ishimaru ,  Digh Hisamoto ,  Kan Yasui ,  Shinichiro Kimura

IPC分类号： H01L29/792 ,  G11C16/04

CPC分类号： G11C16/0466 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.

摘要翻译： 在存储单元包括ONO膜的情况下，其包括用于电荷存储的氮化硅膜和位于氮化硅膜上方和下方的氧化膜; 在ONO电影上方的记忆门; 选择栅极，其经由ONO膜与存储栅的侧表面相邻; 位于选择门下方的栅极绝缘体; 源区; 和漏极区域，通过将BTBT产生的空穴注入氮化硅膜，同时向源极区域施加正电位，向存储栅极施加负电位，向选择栅极施加正电位，进行擦除操作，以及 使电流从漏极区域流向源极区域，从而改善非易失性半导体存储器件的特性。

公开(公告)号：US08064261B2

公开(公告)日：2011-11-22

申请号：US12787158

申请日：2010-05-25

申请人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

发明人： Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru ,  Shinichiro Kimura ,  Daisuke Okada

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0425 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/3459

摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.

摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅结构的半导体非易失性存储器件中进行热孔注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。

公开(公告)号：US07872298B2

公开(公告)日：2011-01-18

申请号：US11777812

申请日：2007-07-13

申请人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

发明人： Yasuhiro Shimamoto ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shinichiro Kimura

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  G11C16/0425 ,  H01L21/28282 ,  H01L21/31155 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/66833

摘要： Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.

摘要翻译： 提高了包括非易失性存储器的半导体器件的性能和可靠性。 非易失性存储器的存储单元包括在半导体衬底的上部上的经由第一电介质膜形成的选择栅电极和通过由具有电荷的ONO多层膜形成的第二电介质膜形成的存储栅电极 存储功能。 第一介质膜用作栅极电介质膜，并且包括由氧化硅或氮氧化硅制成的第三电介质膜和由选择栅电极和第三电极之间形成的金属氧化物或金属硅酸盐构成的含金属元素层 电介质膜。 位于存储栅电极下方的半导体区域和第二电介质膜的电荷密度低于位于选择栅电极和第一电介质膜下方的半导体区域的电荷密度。

公开(公告)号：US07671404B2

公开(公告)日：2010-03-02

申请号：US11589095

申请日：2006-10-30

申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC分类号： H01L29/94

CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。