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    Method and system for generation and distribution of supply voltages in memory systems
    92.
    发明授权
    Method and system for generation and distribution of supply voltages in memory systems 有权
    用于存储器系统中电源电压的生成和分配的方法和系统

    公开(公告)号：US06434044B1

    公开(公告)日：2002-08-13

    申请号：US09788120

    申请日：2001-02-16

    申请人： Geoffrey Steven Gongwer ,  Kevin M. Conley ,  Chi-Ming Wang ,  Yong Liang Wang ,  Raul Adrian Cernea

    发明人： Geoffrey Steven Gongwer ,  Kevin M. Conley ,  Chi-Ming Wang ,  Yong Liang Wang ,  Raul Adrian Cernea

    IPC分类号： G11C1604

    CPC分类号： G11C5/14

    摘要： Techniques for producing and supplying various voltage levels within a memory system having multiple memory blocks (e.g., memory chips) are described. The various voltage levels can be produced by voltage generation circuitry (e.g., charge pump and/or regulator circuitry) within the memory system. The various voltage levels can be supplied to the multiple memory blocks through a power bus. According to one aspect, charge pump and/or regulator circuits are provided within at most one of the memory blocks of a memory system (unless back-ups are provided for fault tolerance), and a power bus is used to distribute the generated voltage levels to other of the memory blocks. According to another aspect, a memory controller generates multiple supply voltage levels that are distributed (e.g., via a power bus) to each of the memory blocks.

    摘要翻译： 描述了在具有多个存储器块（例如，存储器芯片）的存储器系统内产生和提供各种电压电平的技术。 各种电压电平可以由存储器系统内的电压产生电路（例如电荷泵和/或调节器电路）产生。 各种电压电平可以通过电源总线提供给多个存储器块。 根据一个方面，电荷泵和/或调节器电路设置在存储器系统的至多一个存储器块内（除非提供用于容错的备用），并且使用电源总线来分配所产生的电压电平 到其他内存块。 根据另一方面，存储器控制器产生多个电源电压电平，其被分配（例如，经由电源总线）到每个存储器块。

    Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks
    93.
    发明授权
    Flash eeprom system with simultaneous multiple data sector programming and storage of physical block characteristics in other designated blocks 有权
    闪存eeprom系统具有同时多个数据扇区编程和存储其他指定块中的物理块特性

    公开(公告)号：US06426893B1

    公开(公告)日：2002-07-30

    申请号：US09505555

    申请日：2000-02-17

    申请人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

    发明人： Kevin M. Conley ,  John S. Mangan ,  Jeffrey G. Craig

    IPC分类号： G11C1604

    CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

    摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

    摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

    Zone boundary adjustments for defects in non-volatile memories
    95.
    发明授权
    Zone boundary adjustments for defects in non-volatile memories 有权

    公开(公告)号：US09665478B2

    公开(公告)日：2017-05-30

    申请号：US11552227

    申请日：2006-10-24

    申请人： Kevin M. Conley

    发明人： Kevin M. Conley

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/02 ,  G11C29/44 ,  G11C29/00 ,  G11C16/04

    CPC分类号： G06F12/0246 ,  G11C16/04 ,  G11C29/4401 ,  G11C29/76 ,  G11C29/808

    摘要： A non-volatile memory is divided into logical zones by the card controller in order reduce the size of the data structures it uses for address translation. Zone boundaries are adjusted to accommodate defects allowed by memory test to improve card yields and to adjust boundaries in the field to extend the usable lifetime of the card. Firmware scans for the presence of defective blocks on the card. Once the locations of these blocks are known, the firmware calculates the zone boundaries in such a way that good blocks are equally distributed among the zones. Since the number of good blocks meets the card test criteria by the memory test criteria, defects will reduce card yield fallout. The controller can perform dynamic boundary adjustments. When defects occur, the controller can perform the analysis again and, if needed, redistributes the zone boundaries, moving any user data.

    Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks
    96.
    发明申请
    Flash EEPROM System with Simultaneous Multiple Data Sector Programming and Storage of Physical Block Characteristics in Other Designated Blocks 有权
    闪存EEPROM系统，具有同时多个数据扇区编程和存储其他指定块中的物理块特性

    公开(公告)号：US20120294084A1

    公开(公告)日：2012-11-22

    申请号：US13550157

    申请日：2012-07-16

    申请人： Kevin M. Conley ,  John S, Mangan ,  Jeffrey G. Craig

    发明人： Kevin M. Conley ,  John S, Mangan ,  Jeffrey G. Craig

    IPC分类号： G11C16/04

    CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

    摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

    摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

    Partial block data programming and reading operations in a non-volatile memory
    97.
    发明授权
    Partial block data programming and reading operations in a non-volatile memory 有权
    非易失性存储器中的部分块数据编程和读取操作

    公开(公告)号：US08316177B2

    公开(公告)日：2012-11-20

    申请号：US13168756

    申请日：2011-06-24

    申请人： Kevin M. Conley

    发明人： Kevin M. Conley

    IPC分类号： G06F12/00

    CPC分类号： G11C16/102 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/7202 ,  G06F2212/7208 ,  G06F2212/7209 ,  G11C16/105 ,  G11C2216/16

    摘要： Data in less than all of the pages of a non-volatile memory block are updated by programming the new data in unused pages of either the same or another block. In order to prevent having to copy unchanged pages of data into the new block, or to program flags into superceded pages of data, the pages of new data are identified by the same logical address as the pages of data which they superceded and a time stamp is added to note when each page was written. When reading the data, the most recent pages of data are used and the older superceded pages of data are ignored. This technique is also applied to metablocks that include one block from each of several different units of a memory array, by directing all page updates to a single unused block in one of the units.

    摘要翻译： 通过对相同或另一块的未使用页面中的新数据进行编程来更新少于非易失性存储器块的所有页面中的数据。 为了防止不必要将不变的数据页复制到新的块中，或者将标记编程到被替换的数据页面中，新数据的页面被与它们所取代的数据页面相同的逻辑地址标识，并且时间戳 当每个页面被写入时都会添加注释。 当读取数据时，将使用最新的数据页面，并忽略较旧的旧版数据页面。 通过将所有页面更新指向一个单元中的单个未使用的块，该技术也应用于包含来自存储器阵列的几个不同单元中的每一个的一个块的元区块。

    Flash Memory Data Correction and Scrub Techniques
    99.
    发明申请
    Flash Memory Data Correction and Scrub Techniques 有权
    闪存数据校正和擦写技术

    公开(公告)号：US20110055468A1

    公开(公告)日：2011-03-03

    申请号：US12945000

    申请日：2010-11-12

    申请人： Carlos J. Gonzalez ,  Kevin M. Conley

    发明人： Carlos J. Gonzalez ,  Kevin M. Conley

    IPC分类号： G06F12/00 ,  G06F12/02

    CPC分类号： G06F11/106 ,  G06F11/1068 ,  G11C8/08

    摘要： In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

    摘要翻译： 为了保持存储在闪速存储器中的数据的完整性，其易于被存储器的相邻区域中的操作干扰，干扰事件导致在变得如此损坏之前读取，校正和重新写入数据，使得有效数据不能 被收回。 当存储器系统具有执行其他高优先级操作时，通过推迟执行某些纠正措施来平衡维护数据完整性和系统性能的有时冲突的需求。 在使用非常大的擦除单位的存储器系统中，以与有效地重写远远小于擦除单位的容量的数据量相一致的方式执行校正处理。

    Convolutional coding methods for nonvolatile memory
    100.
    发明授权
    Convolutional coding methods for nonvolatile memory 有权
    非易失性存储器的卷积编码方法

    公开(公告)号：US07840875B2

    公开(公告)日：2010-11-23

    申请号：US11383401

    申请日：2006-05-15

    申请人： Kevin M. Conley

    发明人： Kevin M. Conley

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G06F11/1068 ,  G11C7/02 ,  G11C7/1006 ,  G11C2029/0409

    摘要： Data are encoded using convolutional coding prior to storage in a nonvolatile memory array, so that errors that occur when the data are read may be corrected even where there is a large number of such errors. Coding rates of less than one increase the amount of data to be stored but allow correction of large numbers of errors.

    摘要翻译： 在存储在非易失性存储器阵列中之前，使用卷积编码对数据进行编码，从而即使存在大量的这种错误也可以校正当读取数据时发生的错误。 小于1的编码速率增加要存储的数据量，但允许校正大量错误。