公开(公告)号：US08105929B2

公开(公告)日：2012-01-31

申请号：US12193538

申请日：2008-08-18

申请人： Harry Chuang ,  Kong-Beng Thei

发明人： Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L21/38

CPC分类号： H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L29/4966 ,  Y10S438/917

摘要： A method of forming semiconductor structures comprises following steps. A gate dielectric layer is formed over a substrate in an active region. A gate electrode layer is formed over the gate dielectric layer. A first photo resist is formed over the gate electrode layer. The gate electrode layer and dielectric layer are etched thereby forming gate structures and dummy patterns, wherein at least one of the dummy patterns has at least a portion in the active region. The first photo resist is removed. A second photo resist is formed covering the gate structures. The dummy patterns unprotected by the second photo resist are removed. The second photo resist is then removed.

摘要翻译： 形成半导体结构的方法包括以下步骤。 在有源区中的衬底上形成栅介电层。 栅极电极层形成在栅极介电层上。 在栅电极层上形成第一光刻胶。 蚀刻栅极电极层和电介质层，从而形成栅极结构和虚拟图案，其中虚拟图案中的至少一个具有活性区域中的至少一部分。 第一张光刻胶被去除。 形成覆盖栅极结构的第二光致抗蚀剂。 去除不受第二光致抗蚀剂保护的虚拟图案。 然后移除第二个光刻胶。

公开(公告)号：US08058119B2

公开(公告)日：2011-11-15

申请号：US12536878

申请日：2009-08-06

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/66545

摘要： The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes forming a high k dielectric material layer on a semiconductor substrate; forming a conductive material layer on the high k dielectric material layer; forming a dummy gate in a n-type field-effect transistor (nFET) region and a second dummy gate in a pFET region employing polysilicon; forming an inter-level dielectric (ILD) material on the semiconductor substrate; applying a first chemical mechanical polishing (CMP) process to the semiconductor substrate; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a n-type metal to the first gate trench; applying a second CMP process to the semiconductor substrate; removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a p-type metal to the second gate trench; and applying a third CMP process to the semiconductor substrate.

摘要翻译： 本公开提供了制造半导体器件的金属栅叠层的方法。 该方法包括在半导体衬底上形成高k电介质材料层; 在所述高k电介质材料层上形成导电材料层; 在n型场效应晶体管（nFET）区域中形成伪栅极，在使用多晶硅的pFET区域中形成第二伪栅极; 在所述半导体衬底上形成层间电介质（ILD）材料; 对半导体衬底施加第一化学机械抛光（CMP）工艺; 从第一伪栅极去除多晶硅，产生第一栅极沟槽; 在第一栅极沟槽上形成n型金属; 对所述半导体衬底施加第二CMP工艺; 从第二伪栅极去除多晶硅，产生第二栅极沟槽; 在所述第二栅极沟槽中形成p型金属; 以及对所述半导体衬底施加第三CMP处理。

公开(公告)号：US08017473B2

公开(公告)日：2011-09-13

申请号：US12791656

申请日：2010-06-01

申请人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

发明人： Chun-Yi Lee ,  Harry Chuang ,  Ping-Wei Wang ,  Kong-Beng Thei

IPC分类号： H01L21/8238

CPC分类号： H01L27/0883 ,  G11C11/412 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848 ,  Y10S438/919

摘要： A semiconductor structure comprising an SRAM/inverter cell and a method for forming the same are provided, wherein the SRAM/inverter cell has an improved write margin. The SRAM/inverter cell includes a pull-up PMOS device comprising a gate dielectric over the semiconductor substrate, a gate electrode on the gate dielectric wherein the gate electrode comprises a p-type impurity and an n-type impurity, and a stressor formed in a source/drain region. The device drive current of the pull-up PMOS device is reduced due to the counter-doping of the gate electrode.

摘要翻译： 提供了包括SRAM /反相器单元的半导体结构及其形成方法，其中SRAM /反相器单元具有改善的写入裕度。 SRAM /反相器单元包括上拉PMOS器件，其包括半导体衬底上的栅极电介质，栅极电介质上的栅电极，其中栅电极包括p型杂质和n型杂质，以及形成在 源极/漏极区域。 上拉PMOS器件的器件驱动电流由于栅电极的反掺杂而降低。

公开(公告)号：US08008145B2

公开(公告)日：2011-08-30

申请号：US12270466

申请日：2008-11-13

申请人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Shun-Jang Liao ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Provided is a method of fabricating a semiconductor device including a high-k metal gate structure. A substrate is provided including a dummy gate structure (e.g., a sacrificial polysilicon gate), a first and second hard mask layer overlie the dummy gate structure. In one embodiment, a strained region is formed on the substrate. After forming the strained region, the second hard mask layer may be removed. A source/drain region may be formed. An ILD layer is then formed on the substrate. A CMP process may planarize the ILD layer using the first hard mask layer as a stop layer. The CMP process may be continued to remove the first hard mask layer. The dummy gate structure is then removed and a metal gate provided.

摘要翻译： 提供一种制造包括高k金属栅极结构的半导体器件的方法。 提供了包括伪栅极结构（例如，牺牲多晶硅栅极），覆盖在虚拟栅极结构上的第一和第二硬掩模层的衬底。 在一个实施例中，在基底上形成应变区域。 形成应变区后，可以除去第二硬掩模层。 可以形成源极/漏极区域。 然后在衬底上形成ILD层。 CMP工艺可以使用第一硬掩模层作为停止层来平坦化ILD层。 CMP工艺可以继续去除第一硬掩模层。 然后去除虚拟栅极结构并提供金属栅极。

公开(公告)号：US20100311231A1

公开(公告)日：2010-12-09

申请号：US12478358

申请日：2009-06-04

申请人： Kong-Beng Thei ,  Harry Chuang ,  Su-Chen Lai ,  Gary Shen

发明人： Kong-Beng Thei ,  Harry Chuang ,  Su-Chen Lai ,  Gary Shen

IPC分类号： H01L21/336 ,  H01L21/306 ,  H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66583

摘要： A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.

摘要翻译： 公开了一种制造半导体器件的方法。 该方法包括提供基板; 在所述衬底上形成一个或多个栅极结构; 在衬底上形成缓冲层，包括在一个或多个栅极结构上; 在缓冲层上形成蚀刻停止层; 在所述蚀刻停止层上形成层间电介质（ILD）层; 以及去除所述缓冲层的一部分，所述蚀刻停止层的一部分以及所述一个或多个栅极结构上的所述ILD层的一部分。

公开(公告)号：US20100155783A1

公开(公告)日：2010-06-24

申请号：US12338632

申请日：2008-12-18

申请人： Oscar M.K. Law ,  Manoj Achyutrao Joshi ,  Kong-Beng Thei ,  Harry Chuang

发明人： Oscar M.K. Law ,  Manoj Achyutrao Joshi ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L25/07 ,  H01L21/8232

CPC分类号： H01L27/11807 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods for standard cell layouts having variable rules for spacing of layers to cell boundaries are disclosed. In one embodiment, a first standard cell layout is provided with a conductive layer having at least two portions spaced apart by a minimum spacing distance, the conductive layer having at least one portion spaced from a cell boundary by a first spacing distance of less than half of the minimum spacing distance; a second standard cell disposed adjacent the first standard cell with at least one second portion of the conductive layer in the second cell disposed adjacent the first portion in the first standard cell and spaced apart from a common cell boundary by a second spacing greater than half of the minimum; wherein the sum of the first and second spacings is at least as great as the minimum spacing. A method for forming standard is disclosed.

摘要翻译： 公开了具有层与单元边界间隔的可变规则的标准单元布局的结构和方法。 在一个实施例中，第一标准单元布局设置有导电层，其具有间隔最小间隔距离的至少两个部分，所述导电层具有至少一个与单元边界隔开的部分，第一间隔距离小于一半 的最小间距; 与所述第一标准单元相邻设置的第二标准单元，所述第二单元中的所述导电层的至少一个第二部分与所述第一标准单元中的所述第一部分相邻设置并且与所述第一标准单元间隔开第二间隔， 最小 其中所述第一和第二间距的总和至少与所述最小间隔一样大。 公开了一种形成标准的方法。

公开(公告)号：US20100059823A1

公开(公告)日：2010-03-11

申请号：US12432926

申请日：2009-04-30

申请人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L23/525 ,  H01L27/10 ,  H01L27/092

CPC分类号： H01L23/5256 ,  H01L21/823878 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is provided which includes a semiconductor substrate, an isolation structure formed in the substrate for isolating an active region of the substrate, the isolation structure being formed of a first material, an active device formed in the active region of the substrate, the active device having a high-k dielectric and metal gate, and a passive device formed in the isolation structure, the passive device being formed of a second material different from the first material and having a predefined resistivity.

摘要翻译： 提供了一种半导体器件，其包括半导体衬底，形成在衬底中用于隔离衬底的有源区的隔离结构，隔离结构由第一材料形成，有源器件形成在衬底的有源区中， 具有高k电介质和金属栅极的有源器件和形成在隔离结构中的无源器件，无源器件由不同于第一材料并具有预定电阻率的第二材料形成。

公开(公告)号：US20100052058A1

公开(公告)日：2010-03-04

申请号：US12401876

申请日：2009-03-11

申请人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

摘要翻译： 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

公开(公告)号：US20100048013A1

公开(公告)日：2010-02-25

申请号：US12536629

申请日：2009-08-06

申请人： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Y. C. Lin

发明人： Kong-Beng Thei ,  Harry Chuang ,  Ryan Chia-Jen Chen ,  Su-Chen Lai ,  Yi-Shien Mor ,  Yi-Hsing Chen ,  Gary Shen ,  Y. C. Lin

IPC分类号： H01L21/28

CPC分类号： H01L21/31645 ,  H01L21/31604 ,  H01L21/823842

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first active region and a second active region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a first metal layer over the capping layer, the first metal layer having a first work function, forming a mask layer over the first metal layer in the first active region, removing the first metal layer and at least a portion of the capping layer in the second active region using the mask layer, and forming a second metal layer over the partially removed capping layer in the second active region, the second metal layer having a second work function.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一有源区和第二有源区的半导体衬底，在半导体衬底上形成高k电介质层，在高k电介质层上形成覆盖层，在覆盖层上形成第一金属层 第一金属层具有第一功函数，在第一有源区中的第一金属层上形成掩模层，使用掩模层去除第一金属层和第二有源区中的覆盖层的至少一部分 并且在所述第二有源区域中的所述部分去除的覆盖层上形成第二金属层，所述第二金属层具有第二功函数。

公开(公告)号：US20090273055A1

公开(公告)日：2009-11-05

申请号：US12503641

申请日：2009-07-15

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。