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91.发明授权Lateral field emission devices for display elements and methods of fabrication 失效用于显示元件的横向场致发射器件和制造方法
公开(公告)号：US5751097A
公开(公告)日：1998-05-12
申请号：US789175
申请日：1997-01-24
CPC分类号： H01J3/022 , H01J2201/30423
摘要： Lateral field emission devices ("FEDs") for display elements and methods of fabrication are set forth. The FED includes a thin-film emitter oriented parallel to, and disposed above, a substrate. The FED further includes a columnar shaped anode having a first lateral surface. A phosphor layer is disposed adjacent to the first lateral surface. Specifically, the anode is oriented such that the lateral surface and adjacent phosphor layer are perpendicular to the substrate. The emitter has a tip which is spaced less than the mean free distance of an electron in air from the phosphor layer. Operationally, when a voltage potential is applied between said anode and said emitter, electrons are emitted from the tip of the emitter into the phosphor layer causing the phosphor layer to emit electromagnetic energy. Further specific details of the field emission device, fabrication method, method of operation, and associated display are set forth.
摘要翻译： 阐述了用于显示元件和制造方法的侧面场致发射器件（“FED”）。 FED包括平行于并设置在基板上方的薄膜发射极。 FED还包括具有第一侧表面的柱状阳极。 磷光体层邻近第一侧面设置。 具体地，阳极被定向成使得侧表面和相邻磷光体层垂直于衬底。 发射器具有一个尖端，该尖端的距离小于空气中的电子与荧光体层的平均自由距离。 在工作上，当在所述阳极和所述发射极之间施加电压电位时，电子从发射极的尖端发射到荧光体层中，从而使荧光层发射电磁能。 阐述了场致发射装置，制造方法，操作方法和相关显示器的进一步具体细节。
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92.发明授权Non-evacuated lateral fed employing emitter-anode spacing less than mean free path distance of an electron in air 失效使用发射极 - 阳极间距的非抽真空横向馈电小于电子在空气中的平均自由程距离
公开(公告)号：US5736810A
公开(公告)日：1998-04-07
申请号：US641252
申请日：1996-04-30
CPC分类号： H01J3/022 , H01J2201/30423
摘要： Lateral field emission devices ("FEDs") for display elements and methods of fabrication are set forth. The FED includes a thin-film emitter oriented parallel to, and disposed above, a substrate. The FED further includes a columnar shaped anode having a first lateral surface. A phosphor layer is disposed adjacent to the first lateral surface. Specifically, the anode is oriented such that the lateral surface and adjacent phosphor layer are perpendicular to the substrate. The emitter has a tip which is spaced less than the mean free distance of an electron in air from the phosphor layer. Operationally, when a voltage potential is applied between said anode and said emitter, electrons are emitted from the tip of the emitter into the phosphor layer causing the phosphor layer to emit electromagnetic energy. Further specific details of the field emission device, fabrication method, method of operation, and associated display are set forth.
摘要翻译： 阐述了用于显示元件和制造方法的侧面场致发射器件（“FED”）。 FED包括平行于并设置在基板上方的薄膜发射极。 FED还包括具有第一侧表面的柱状阳极。 磷光体层邻近第一侧面设置。 具体地，阳极被定向成使得侧表面和相邻磷光体层垂直于衬底。 发射器具有一个尖端，该尖端的距离小于空气中的电子与荧光体层的平均自由距离。 在工作上，当在所述阳极和所述发射极之间施加电压电位时，电子从发射极的尖端发射到荧光体层中，从而使荧光层发射电磁能。 阐述了场致发射装置，制造方法，操作方法和相关显示器的进一步具体细节。
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93.发明授权
公开(公告)号：US5670388A
公开(公告)日：1997-09-23
申请号：US542592
申请日：1995-10-13
IPC分类号： H01L29/786 , H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L2924/0002 , Y10S148/15 , Y10S438/98
摘要： Structures and methods are presented for forming a body-substrate connector for an SOI FET. The connector is formed substantially co-aligned with the gate conductor on a side of the device that does not interfere with source and drain. The body is thus held close to the substrate potential and the connector provides a path for majority carriers to quickly leave the body. By contacting the body of the SOI MOSFET device in a manner that does not perturb the charge imaged by the gate, parasitic bipolar effects are eliminated while maintaining the desirable attributes of SOI MOSFET devices, such as low substrate bias sensitivity and steep sub-threshold slope. By forming the connector substantially co-aligned with the gate conductor the connection uses little or no surface area.
摘要翻译： 提出了用于形成用于SOI FET的体衬底连接器的结构和方法。 该连接器在不干扰源极和漏极的装置的一侧基本上与栅极导体共同对准。 因此，本体保持靠近基底电位，并且连接器为多数载体快速离开身体提供了路径。 通过以不扰乱由栅极成像的电荷的方式接触SOI MOSFET器件的主体，消除寄生双极效应，同时保持SOI MOSFET器件的期望属性，例如低衬底偏置灵敏度和陡峭的次阈值斜率 。 通过形成与栅极导体基本上共同对准的连接器，连接使用很少或没有表面积。
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公开(公告)号：US07911025B2
公开(公告)日：2011-03-22
申请号：US12127080
申请日：2008-05-27
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。
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公开(公告)号：US07863122B2
公开(公告)日：2011-01-04
申请号：US12133440
申请日：2008-06-05
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
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96.发明授权Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法公开(公告)号：US07692250B2
公开(公告)日：2010-04-06
申请号：US11927110
申请日：2007-10-29
IPC分类号： H01L27/12
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。
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公开(公告)号：US07667248B2
公开(公告)日：2010-02-23
申请号：US12028916
申请日：2008-02-11
IPC分类号： H01L29/00
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
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98.发明授权公开(公告)号：US07648869B2
公开(公告)日：2010-01-19
申请号：US11330689
申请日：2006-01-12
申请人： Shunhua Thomas Chang , Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Shunhua Thomas Chang , Toshiharu Furukawa , Robert J. Gauthier, Jr. , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/8238
CPC分类号： H01L27/0921 , H01L21/823878
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The structure comprises a first doped well formed in a substrate of semiconductor material, a second doped well formed in the substrate proximate to the first doped well, and a deep trench defined in the substrate. The deep trench includes sidewalls positioned between the first and second doped wells. A buried conductive region is defined in the semiconductor material bordering the base and the sidewalls of the deep trench. The buried conductive region intersects the first and second doped wells. The buried conductive region has a higher dopant concentration than the first and second doped wells. The buried conductive region may be formed by solid phase diffusion from a mobile dopant-containing material placed in the deep trench. After the buried conductive region is formed, the mobile dopant-containing material may optionally remain in the deep trench.
摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体结构和方法。 该结构包括在半导体材料的衬底中形成的第一掺杂阱，在衬底中形成的靠近第一掺杂阱的第二掺杂阱以及限定在衬底中的深沟槽。 深沟槽包括位于第一和第二掺杂阱之间的侧壁。 在与深沟槽的基底和侧壁相邻的半导体材料中限定掩埋导电区域。 埋入的导电区域与第一和第二掺杂阱相交。 掩埋导电区域具有比第一和第二掺杂阱更高的掺杂剂浓度。 掩埋导电区域可以通过从放置在深沟槽中的含有移动掺杂剂的材料的固相扩散形成。 在形成掩埋导电区域之后，含有移动掺杂剂的材料可以任选地保留在深沟槽中。
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99.发明授权公开(公告)号：US07645676B2
公开(公告)日：2010-01-12
申请号：US11927135
申请日：2007-10-29
申请人： Toshiharu Furukawa , Robert J. Gauthier , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
发明人： Toshiharu Furukawa , Robert J. Gauthier , David Vaclav Horak , Charles William Koburger, III , Jack Allan Mandelman , William Robert Tonti
IPC分类号： H01L21/76
CPC分类号： H01L21/76237 , H01L21/26533 , H01L21/76213 , H01L21/76229 , H01L21/76232 , H01L21/823878 , H01L27/0921 , H01L29/1087 , H01L29/78
摘要： Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises a shaped-modified isolation region that is formed in a trench generally between two doped wells of the substrate in which the bulk CMOS devices are fabricated. The shaped-modified isolation region may comprise a widened dielectric-filled portion of the trench, which may optionally include a nearby damage region, or a narrowed dielectric-filled portion of the trench that partitions a damage region between the two doped wells. Latch-up may also be suppressed by providing a lattice-mismatched layer between the trench base and the dielectric filler in the trench.
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公开(公告)号：US07470929B2
公开(公告)日：2008-12-30
申请号：US11491721
申请日：2006-07-24
IPC分类号： H01L29/10
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.
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