公开(公告)号：US20180145052A1

公开(公告)日：2018-05-24

申请号：US15574822

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Peter G. TOLCHINSKY ,  Robert S. CHAU

IPC: H01L25/065 ,  H01L27/06 ,  H01L27/092 ,  H01L23/48 ,  H01L29/20 ,  H01L29/778 ,  H01L25/00 ,  H01L21/8252 ,  H01L21/8238 ,  H01L21/02

Abstract: GaN-On-Silicon (GOS) structures and techniques for accommodating and/or controlling stress/strain incurred during III-N growth on a large diameter silicon substrate. A back-side of a silicon substrate may be processed to adapt substrates of standardized diameters and thicknesses to GOS applications. Bowing and/or warping during high temperature epitaxial growth processes may be mitigated by pre-processing silicon substrate so as to pre-stress the substrate in a manner than counterbalances stress induced by the III-N material and/or improve a substrate's ability to absorb stress. III-N devices fabricated on an engineered GOS substrate may be integrated together with silicon MOS devices fabricated on a separate substrate. Structures employed to improve substrate resilience and/or counterbalance the substrate stress induced by the III-N material may be further employed for interconnecting the III-N and silicon MOS devices of a 3D IC.

公开(公告)号：US20170236928A1

公开(公告)日：2017-08-17

申请号：US15499774

申请日：2017-04-27

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L21/30612 ,  H01L21/30617 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

公开(公告)号：US20160056244A1

公开(公告)日：2016-02-25

申请号：US14779257

申请日：2013-06-28

Applicant: INTEL CORPORATION

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Sanaz K. GARDNER ,  Benjamin CHU-KUNG ,  Marko RADOSAVLJEVIC ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/04 ,  H01L21/324 ,  H01L29/06 ,  H01L21/02 ,  H01L21/308

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/324 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0684

Abstract: A fin over an insulating layer on a substrate having a first crystal orientation is modified to form a surface aligned along a second crystal orientation. A device layer is deposited over the surface of the fin aligned along the second crystal orientation.

Abstract translation: 在具有第一晶体取向的基板上的绝缘层上的鳍被修改以形成沿着第二晶体取向对准的表面。 器件层沉积在沿着第二晶体取向对准的鳍片的表面上。

公开(公告)号：US20150318375A1

公开(公告)日：2015-11-05

申请号：US14752365

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Niloy MUKHERJEE ,  Niti GOEL ,  Sanaz Kabehie GARDNER ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Robert S. CHAU

IPC: H01L29/66 ,  H01L29/205 ,  H01L21/223 ,  H01L21/02 ,  H01L29/08 ,  H01L21/265 ,  H01L29/20 ,  H01L21/311

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

Abstract translation: 实施例包括高电子迁移率晶体管（HEMT）。 在实施例中，栅电极与源极和漏极半导体区间隔开不同的距离以提供高击穿电压和低导通状态电阻。 在实施例中，应用自对准技术以在沟槽中和在中间心轴上形成电介质衬垫，以通过单个掩蔽操作独立地限定栅极长度，栅极源长度和栅极 - 漏极长度。 在实施例中，III-N HEMT包括用于阈值电压调谐和/或增强模式操作的氟掺杂半导体势垒层。

公开(公告)号：US20150108496A1

公开(公告)日：2015-04-23

申请号：US14581722

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Sanaz GARDNER ,  Seung Hoon SUNG ,  Robert S. Chau

IPC: H01L27/12 ,  H01L29/201 ,  H01L29/06 ,  H01L21/285 ,  H01L29/66 ,  H01L21/84 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/0228 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/201 ,  H01L29/42356 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/802

Abstract: A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall. In embodiments, the silicon fin has a width comparable to the III-N epitaxial film thicknesses for a more compliant seeding layer, permitting lower defect density and/or reduced epitaxial film thickness. In embodiments, a transition layer is GaN and the semiconductor channel comprises Indium (In) to increase a conduction band offset from the silicon fin. In other embodiments, the fin is sacrificial and either removed or oxidized, or otherwise converted into a dielectric structure during transistor fabrication. In certain embodiments employing a sacrificial fin, the III-N transition layer and semiconductor channel is substantially pure GaN, permitting a breakdown voltage higher than would be sustainable in the presence of the silicon fin.

Abstract translation: III-N半导体沟道形成在形成于诸如翅片侧壁的硅模板结构的（111）或（110）表面上的III-N过渡层上。 在实施例中，硅鳍具有与更适应的种子层的III-N外延膜厚度相当的宽度，允许更低的缺陷密度和/或降低的外延膜厚度。 在实施例中，过渡层是GaN，并且半导体沟道包括铟（In）以增加从硅片的导带偏移。 在其它实施例中，鳍是牺牲性的，并且在晶体管制造期间被去除或氧化，或以其它方式转换为电介质结构。 在采用牺牲散热片的某些实施例中，III-N过渡层和半导体通道是基本上纯的GaN，允许击穿电压高于在硅片存在时可持续的击穿电压。