公开(公告)号：US20190148533A1

公开(公告)日：2019-05-16

申请号：US16242949

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

公开(公告)号：US20180315659A1

公开(公告)日：2018-11-01

申请号：US15528031

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC: H01L21/8252 ,  H01L33/00 ,  H01L33/08 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32

CPC classification number: H01L21/8252 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/08 ,  H01L33/10 ,  H01L33/12 ,  H01L33/24 ,  H01L33/32 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed toward an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate and a buffer layer disposed over the semiconductor substrate. The buffer layer may have a plurality of openings formed therein. In embodiments, the IC die may further include a plurality of group III-Nitride structures. Individual group III-Nitride structures of the plurality of group III-Nitride structures may include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening. In embodiments, the upper portion may include a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening. Other embodiments may be described and/or claimed.

公开(公告)号：US20170352532A1

公开(公告)日：2017-12-07

申请号：US15527287

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Robert S. CHAU ,  Sanaz K. GARDNER ,  Seung Hoon SUNG

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/8258 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/32 ,  H01L29/225 ,  H01L29/205 ,  H01L29/20 ,  H01L29/08 ,  H01L29/778 ,  H01L29/22 ,  H01L27/092 ,  H01L23/00

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02551 ,  H01L21/02554 ,  H01L21/02557 ,  H01L21/0256 ,  H01L21/02562 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0274 ,  H01L21/8258 ,  H01L23/48 ,  H01L24/16 ,  H01L25/065 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/2203 ,  H01L29/225 ,  H01L29/267 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66969 ,  H01L29/7786 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170271448A1

公开(公告)日：2017-09-21

申请号：US15598290

申请日：2017-05-17

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Sherry R. TAFT ,  Van H. LE ,  Sansaptak DASGUPTA ,  Seung Hoon SUNG ,  Sanaz K. GARDNER ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L29/1037 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/02639 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/2003 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.

公开(公告)号：US20210202374A1

公开(公告)日：2021-07-01

申请号：US17202281

申请日：2021-03-15

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/764 ,  H01L21/768 ,  H01L29/06 ,  H01L23/532

Abstract: Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

公开(公告)号：US20180261498A1

公开(公告)日：2018-09-13

申请号：US15779442

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L21/768 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

Abstract: Related fields of the present disclosure are in the field of transistor devices, and in particular, FinFET device structures formed using aspect ratio trapping trench (ART) process techniques. For example, a FinFET device consistent with the present disclosure comprises a first fin structure including a first upper fin portion atop a first lower fin portion and a second fin structure including a second upper fin portion atop a second lower fin portion. The first and second upper fin structures include a Group IV material and the first and second lower fin structures include a Group III-V material.

公开(公告)号：US20180226496A1

公开(公告)日：2018-08-09

申请号：US15771998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/267 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/107 ,  H01L29/1079 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

公开(公告)号：US20180190807A1

公开(公告)日：2018-07-05

申请号：US15567579

申请日：2015-05-19

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Han Wui THEN ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/205 ,  H01L21/02 ,  H01L21/8258

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02647 ,  H01L21/823431 ,  H01L21/8252 ,  H01L21/8258 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462

Abstract: Semiconductor devices including an elevated or raised doped crystalline structure extending from a device layer are described. In embodiments, III-N transistors include raised crystalline n+ doped source/drain structures on either side of a gate stack. In embodiments, an amorphous material is employed to limit growth of polycrystalline source/drain material, allowing a high quality source/drain doped crystal to grow from an undamaged region and laterally expand to form a low resistance interface with a two-degree electron gas (2DEG) formed within the device layer. In some embodiments, regions of damaged GaN that may spawn competitive polycrystalline overgrowths are covered with the amorphous material prior to commencing raised source/drain growth.

公开(公告)号：US20180145164A1

公开(公告)日：2018-05-24

申请号：US15574817

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sanaz K. GARDNER ,  Seung Hoon SUNG ,  Robert S. CHAU

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L21/04

CPC classification number: H01L29/7786 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/0445 ,  H01L21/8258 ,  H01L27/085 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/785

Abstract: Crystalline heterostructures including an elevated crystalline structure extending from one or more trenches in a trench layer disposed over a crystalline substrate are described. In some embodiments, an interfacial layer is disposed over a silicon substrate surface. The interfacial layer facilitates growth of the elevated structure from a bottom of the trench at growth temperatures that may otherwise degrade the substrate surface and induce more defects in the elevated structure. The trench layer may be disposed over the interfacial layer with a trench bottom exposing a portion of the interfacial layer. Arbitrarily large merged crystal structures having low defect density surfaces may be overgrown from the trenches. Devices, such as III-N transistors, may be further formed on the raised crystalline structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate.

公开(公告)号：US20170263706A1

公开(公告)日：2017-09-14

申请号：US15529481

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia M. RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.