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    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP
    3.
    发明申请
    SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH REDUCED CAP 有权

    公开(公告)号：US20220310818A1

    公开(公告)日：2022-09-29

    申请号：US17211751

    申请日：2021-03-24

    Applicant: Intel Corporation

    Inventor： Seung Hoon SUNG ,  Tristan TRONIC ,  Szuya S. LIAO ,  Jack T. KAVALIEROS

    IPC: H01L29/49 ,  H01L23/535 ,  H01L27/092 ,  H01L21/28 ,  H01L21/8238

    Abstract: Self-aligned gate endcap (SAGE) architectures with reduced or removed caps, and methods of fabricating self-aligned gate endcap (SAGE) architectures with reduced or removed caps, are described. In an example, an integrated circuit structure includes a first gate electrode over a first semiconductor fin. A second gate electrode is over a second semiconductor fin. A gate endcap isolation structure is between the first gate electrode and the second gate electrode, the gate endcap isolation structure having a higher-k dielectric cap layer on a lower-k dielectric wall. A local interconnect is on the first gate electrode, on the higher-k dielectric cap layer, and on the second gate electrode, the local interconnect having a bottommost surface above an uppermost surface of the higher-k dielectric cap layer.

    METAL-ASSISTED SINGLE CRYSTAL TRANSISTORS
    4.
    发明申请
    METAL-ASSISTED SINGLE CRYSTAL TRANSISTORS 有权

    公开(公告)号：US20220216347A1

    公开(公告)日：2022-07-07

    申请号：US17701232

    申请日：2022-03-22

    Applicant: Intel Corporation

    Inventor： Van H. LE ,  Ashish AGRAWAL ,  Seung Hoon SUNG ,  Abhishek A. SHARMA ,  Ravi PILLARISETTY

    IPC: H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

    Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

    FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE
    5.
    发明申请
    FORKSHEET TRANSISTORS WITH DIELECTRIC OR CONDUCTIVE SPINE 有权

    公开(公告)号：US20220093647A1

    公开(公告)日：2022-03-24

    申请号：US17030226

    申请日：2020-09-23

    Applicant: Intel Corporation

    Inventor： Seung Hoon SUNG ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC ,  Christopher M. NEUMANN ,  Susmita GHOSE ,  Varun MISHRA ,  Cory WEBER ,  Stephen M. CEA ,  Tahir GHANI ,  Jack T. KAVALIEROS

    IPC: H01L27/12 ,  H01L21/84

    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.

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