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公开(公告)号:US20220093547A1
公开(公告)日:2022-03-24
申请号:US17025843
申请日:2020-09-18
Applicant: Intel Corporation
Inventor: Adel A. Elsherbini , Zhiguo Qian , Gerald S. Pasdast , Mohammad Enamul Kabir , Han Wui Then , Kimin Jun , Kevin P. O'Brien , Johanna M. Swan , Shawna M. Liff , Aleksandar Aleksov , Feras Eid
IPC: H01L23/00 , H01L25/065 , H01L49/02
Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
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公开(公告)号:US20210296242A1
公开(公告)日:2021-09-23
申请号:US17340781
申请日:2021-06-07
Applicant: Intel Corporation
Inventor: MD Altaf Hossain , Kevin J. Doran , Yu Amos Zhang , Zhiguo Qian
IPC: H01L23/538 , H01L25/18 , H01L23/498 , H01L23/13 , H01L25/065
Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.
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公开(公告)号:US20210167015A1
公开(公告)日:2021-06-03
申请号:US17114954
申请日:2020-12-08
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Kemal Aygun
IPC: H01L23/538 , H01L23/00 , H01L23/522 , H01L23/528
Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
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公开(公告)号:US10950550B2
公开(公告)日:2021-03-16
申请号:US15774306
申请日:2015-12-22
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Jianyong Xie , Kemal Aygun
IPC: H01L23/12 , H01L23/14 , H01L23/48 , H01L21/4763 , H01L23/538 , H01L21/48 , H01L23/498 , H01L23/00 , H01L25/065
Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.
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公开(公告)号:US20210057321A1
公开(公告)日:2021-02-25
申请号:US17074820
申请日:2020-10-20
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Kemal Aygun , Yu Zhang
IPC: H01L23/498
Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
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公开(公告)号:US10580734B2
公开(公告)日:2020-03-03
申请号:US15773950
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Yu Amos Zhang , Gabriel Regalado Silva , Zhiguo Qian , Kemal Aygun
IPC: H01L23/50 , H01L23/528 , H01L23/498 , H05K1/02 , H01L23/66 , H01L23/00 , H01R13/6471
Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance. This package device provides higher frequency and more accurate data signal transfer between different horizontal locations of the data signal transmission lines, and thus also between devices such as integrated circuit (IC) chips attached to the package device.
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公开(公告)号:US20190318993A1
公开(公告)日:2019-10-17
申请号:US16469084
申请日:2016-12-28
Applicant: Intel Corporation
Inventor: Ravindranath V. Mahajan , Zhiguo Qian , Henning Braunisch , Kemal Aygun , Sujit Sharan
IPC: H01L23/538 , H01L25/065 , H01L23/498 , H01L25/00
Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.
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公开(公告)号:US10396036B2
公开(公告)日:2019-08-27
申请号:US15774257
申请日:2015-12-26
Applicant: Intel Corporation
Inventor: Yu Amos Zhang , Zhiguo Qian , Kemal Aygun , Yidnekachew S. Mekonnen , Gregorio R. Murtagian , Sanka Ganesan , Eduard Roytman , Jeff C. Morriss
IPC: H01L23/48 , H01L23/538 , H01L23/552 , H01L23/66 , H01L23/498 , H01L23/50 , H01L25/065
Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia). The ground shielding for the electro-optical module may include patterns of ground isolation shielding attachments and contacts.
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公开(公告)号:US20190229058A1
公开(公告)日:2019-07-25
申请号:US16336582
申请日:2016-09-29
Applicant: Intel Corporation
Inventor: Zhiguo Qian , Kemal Aygun
IPC: H01L23/538 , H01L23/528 , H01L23/522 , H01L23/00
Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.
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公开(公告)号:US10317932B2
公开(公告)日:2019-06-11
申请号:US15201422
申请日:2016-07-02
Applicant: Intel Corporation
Inventor: Zhichao Zhang , Xiang Li , Kemal Aygun , Zhiguo Qian , Tolga Memioglu
Abstract: One embodiment provides an apparatus. The apparatus includes a dual in-line memory module (DIMM). The DIMM includes at least one memory module integrated circuit (IC); a DIMM printed circuit board (PCB); a plurality of DIMM PCB contacts; and a capacitive structure. Each DIMM PCB contact is to couple the memory module IC to a respective DIMM connector pin. The capacitive structure is to provide a mutual capacitance between a first DIMM connector signal pin and a second DIMM connector signal pin.
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