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    SIDE MOUNTED INTERCONNECT BRIDGES
    92.
    发明申请
    SIDE MOUNTED INTERCONNECT BRIDGES 有权

    公开(公告)号：US20210296242A1

    公开(公告)日：2021-09-23

    申请号：US17340781

    申请日：2021-06-07

    Applicant: Intel Corporation

    Inventor： MD Altaf Hossain ,  Kevin J. Doran ,  Yu Amos Zhang ,  Zhiguo Qian

    IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498 ,  H01L23/13 ,  H01L25/065

    Abstract: A device and method of utilizing an interconnect bridge to electrically couple two semiconductor dies located on different surfaces. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a substrate to a semiconductor die on a motherboard are shown. Integrated circuit packages using an interconnect bridge to electrically couple a semiconductor die on a top surface of a substrate to a semiconductor die on a bottom surface of a substrate are shown. Methods of electrically coupling semiconductor dies on different surfaces using interconnect bridges are shown.

    DIE INTERCONNECT STRUCTURES AND METHODS
    93.
    发明申请
    DIE INTERCONNECT STRUCTURES AND METHODS 有权

    公开(公告)号：US20210167015A1

    公开(公告)日：2021-06-03

    申请号：US17114954

    申请日：2020-12-08

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528

    Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

    Semiconductor package with through bridge die connections
    94.
    发明授权
    Semiconductor package with through bridge die connections 有权

    公开(公告)号：US10950550B2

    公开(公告)日：2021-03-16

    申请号：US15774306

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Jianyong Xie ,  Kemal Aygun

    IPC: H01L23/12 ,  H01L23/14 ,  H01L23/48 ,  H01L21/4763 ,  H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

    Abstract: Semiconductor packages with through bridge die connections and a method of manufacture therefor is disclosed. The semiconductor packages may house one or more electronic components as a system in a package (SiP) implementation. A bridge die, such as an embedded multi-die interconnect bridge (EMIB), may be embedded within one or more build-up layers of the semiconductor package. The bridge die may have an electrically conductive bulk that may be electrically connected on a backside to a power plane and used to deliver power to one or more dies attached to the semiconductor package via interconnects formed on a topside of the bridge die that are electrically connected to the bulk of the bridge die. A more direct path for power delivery through the bridge die may be achieved compared to routing power around the bridge die.

    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
    95.
    发明申请
    GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION 有权

    公开(公告)号：US20210057321A1

    公开(公告)日：2021-02-25

    申请号：US17074820

    申请日：2020-10-20

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun ,  Yu Zhang

    IPC: H01L23/498

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.

    DIE INTERCONNECT STRUCTURES AND METHODS
    99.
    发明申请
    DIE INTERCONNECT STRUCTURES AND METHODS 审中-公开

    公开(公告)号：US20190229058A1

    公开(公告)日：2019-07-25

    申请号：US16336582

    申请日：2016-09-29

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Kemal Aygun

    IPC: H01L23/538 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

    Abstract: Generally discussed herein are systems, devices, and methods to reduce crosstalk interference. An interconnect structure can include a first metal layer, a second metal layer, a third metal layer, the first metal layer closer to the first and second dies than the second and third metal layers, the first metal layer including a ground plane within a footprint of a bump field of the interconnect structure and signal traces outside the footprint of the bump field.

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