公开(公告)号：US11683941B2

公开(公告)日：2023-06-20

申请号：US16701194

申请日：2019-12-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alexander Reznicek ,  Karthik Balakrishnan ,  Bahman Hekmatshoartabari ,  Takashi Ando

IPC: H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/34 ,  H10N70/066 ,  H10N70/24 ,  H10N70/821 ,  H10N70/841

Abstract: A semiconductor structure may include two vertical transport field effect transistors comprising a top source drain, a bottom source drain, and an epitaxial channel and a resistive random access memory between the two vertical transport field effect transistors, the resistive random access memory may include an oxide layer, a top electrode, and a bottom electrode, wherein the oxide layer may contact the top source drain of the two vertical field effect transistor. The top source drain may function as the bottom electrode of the resistive random access memory. The semiconductor structure may include a shallow trench isolation between the two vertical transport field effect transistors, the shallow trench isolation may be embedded in a first spacer, a doped source, and a portion of a substrate.

公开(公告)号：US11678591B2

公开(公告)日：2023-06-13

申请号：US17037109

申请日：2020-09-29

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Karthik Balakrishnan ,  Jeffrey Sleight ,  David James Frank

IPC: H01L39/04 ,  H01L39/02 ,  G06N10/00 ,  H01L39/24 ,  H01L39/22

CPC classification number: H01L39/025 ,  G06N10/00 ,  H01L39/04 ,  H01L39/223 ,  H01L39/2493

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

公开(公告)号：US20220102613A1

公开(公告)日：2022-03-31

申请号：US17037191

申请日：2020-09-29

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Karthik Balakrishnan ,  Jeffrey Sleight ,  David James Frank

IPC: H01L39/24 ,  H01L39/08 ,  H01L39/04 ,  H01L27/18

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

公开(公告)号：US20220102612A1

公开(公告)日：2022-03-31

申请号：US17037109

申请日：2020-09-29

Applicant: International Business Machines Corporation

Inventor： Isaac Lauer ,  Karthik Balakrishnan ,  Jeffrey Sleight ,  David James Frank

IPC: H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  G06N10/00

Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

公开(公告)号：US20220005936A1

公开(公告)日：2022-01-06

申请号：US17477916

申请日：2021-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Jeng-Bang Yau ,  Alexander Reznicek ,  Tak H. Ning

IPC: H01L29/66 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

公开(公告)号：US11158756B2

公开(公告)日：2021-10-26

申请号：US16572102

申请日：2019-09-16

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Jeng-Bang Yau ,  Karthik Balakrishnan

IPC: H01L31/119 ,  H05G1/28 ,  G01T1/02 ,  H01L29/78 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  G01T7/00

Abstract: A semiconductor radiation monitor (i.e., dosimeter) is provided that has an oxide charge storage region located on a first side of a semiconductor fin and a functional gate structure located on a second side of the semiconductor fin that is opposite the first side. Charges are created in the oxide charge storage region that is located on the first side of the semiconductor fin and detected on the second side of the semiconductor fin by the functional gate structure. Multiple semiconductor fins in parallel can form a dense and very sensitive semiconductor radiation monitor.

公开(公告)号：US11158729B2

公开(公告)日：2021-10-26

申请号：US16671951

申请日：2019-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Jeng-Bang Yau ,  Alexander Reznicek ,  Tak H. Ning

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/66 ,  H01L29/423 ,  H01L27/11521 ,  H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

公开(公告)号：US11061146B2

公开(公告)日：2021-07-13

申请号：US16256409

申请日：2019-01-24

Applicant: International Business Machines Corporation

Inventor： Jeng-Bang Yau ,  Alexander Reznicek ,  Karthik Balakrishnan ,  Bahman Hekmatshoartabari

IPC: G01T1/02 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor radiation monitor is provided that includes a charge storage region composed of a dielectric material nanosheet, such as, for example an epitaxial oxide nanosheet, which is sandwiched between a top semiconductor nanosheet and a bottom semiconductor nanosheet. A functional gate structure is located above the top semiconductor nanosheet and beneath the bottom semiconductor nanosheet.

公开(公告)号：US20210193923A1

公开(公告)日：2021-06-24

申请号：US16723217

申请日：2019-12-20

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Takashi Ando ,  Karthik Balakrishnan

IPC: H01L45/00 ,  H01L27/24

Abstract: A one-transistor-two-resistor (1T2R) resistive random access memory (ReRAM) structure, and a method for forming the same, includes forming a vertical field effect transistor (VFET) including an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing protruding regions of triangular shape bounded by planes that extend horizontally beyond the channel region. A ReRAM stack is conformally deposited on the VFET. The ReRAM stack includes an oxide layer located directly above the epitaxial region, a top electrode layer directly above the oxide layer and a metal fill above the top electrode layer. Each of the two opposing protruding regions of the epitaxial region acts as a bottom electrode for the ReRAM stack.

公开(公告)号：US11018254B2

公开(公告)日：2021-05-25

申请号：US15086542

申请日：2016-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/12 ,  H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L27/082

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.