公开(公告)号：US11664422B2

公开(公告)日：2023-05-30

申请号：US17304021

申请日：2021-06-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Chen Zhang ,  Xin Miao ,  Wenyu Xu

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66553

Abstract: A semiconductor device including a plurality of nanosheet transistor channels adjacent to a source/drain. An inner spacer located between each of the plurality of nanosheet transistor channels and the inner spacer wraps around the end of each of the plurality of nanosheet transistors. The source/drain is in contact with the inner spacer and each of the plurality of nanosheet transistor channels. A gate surrounding each of the plurality of nanosheet transistor channels and an electrical contact connected to the source/drain. An ultra low-k spacer located between the gate and the source/drain. The ultra low-k spacer reduces the parasitic capacitance of the nanosheet transistor.

公开(公告)号：US11575042B2

公开(公告)日：2023-02-07

申请号：US16743568

申请日：2020-01-15

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Chen Zhang ,  Kangguo Cheng ,  Wenyu Xu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/207 ,  H01L29/66

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

公开(公告)号：US11329167B2

公开(公告)日：2022-05-10

申请号：US16736898

申请日：2020-01-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jingyun Zhang ,  Xin Miao ,  Ruilong Xie ,  Alexander Reznicek

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3065

Abstract: A method is presented for reducing sagging effects in nanosheet devices. The method includes forming at least two nanosheet structures over a substrate, wherein each nanosheet structure includes alternating layers of a first semiconductor material and a second semiconductor material, depositing a dielectric layer over the at least two nanosheet structures, depositing a dummy gate over the dielectric layer, etching the first semiconductor material to create voids filled with inner spacers, removing the dummy gate and the dielectric layer such that a supporting dielectric section remains between the at least two nanosheet structures, and removing the etched first semiconductor material such that a supporting structure is defined including the supporting dielectric section and the second semiconductor material.

公开(公告)号：US11222979B2

公开(公告)日：2022-01-11

申请号：US16855472

申请日：2020-04-22

Applicant: International Business Machines Corporation

Inventor： Xin Miao ,  Alexander Reznicek ,  Jingyun Zhang ,  Ruilong Xie

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/165

Abstract: FET devices with bottom dielectric isolation and sidewall implants in the source and drain regions to prevent epitaxial growth below the bottom dielectric isolation are provided. In one aspect, a semiconductor FET device includes: a device stack(s) disposed on a substrate, wherein the device stack(s) includes active layers oriented vertically over a bottom dielectric isolation layer; STI regions embedded in the substrate at a base of the device stack(s), wherein a top surface of the STI regions is recessed below a top surface of the substrate exposing substrate sidewalls under the bottom dielectric isolation region, wherein the sidewalls of the substrate include implanted ions; source and drains on opposite sides of the active layers; and gates surrounding a portion of each of the active layers, wherein the gates are offset from the source and drains by inner spacers. A method of forming a semiconductor FET device is also provided.

公开(公告)号：US11088288B2

公开(公告)日：2021-08-10

申请号：US16570150

申请日：2019-09-13

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Jingyun Zhang ,  Xin Miao ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor structure and formation thereof. The semiconductor structure including: a nano-sheet field-effect transistor; a layer of support material that is located beneath a stack of nano-sheets that are included in the nano-sheet field-effect transistor; and a vertical support that is affixed to a stack of nano-sheets, wherein the vertical support (i) has an end that is affixed to the layer of support material and (ii) a side that is a affixed to at least one nano-sheet of the stack of nano-sheets.

公开(公告)号：US11069800B2

公开(公告)日：2021-07-20

申请号：US16271069

申请日：2019-02-08

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

公开(公告)号：US11062965B2

公开(公告)日：2021-07-13

申请号：US16781183

申请日：2020-02-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/66 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L23/535 ,  H01L29/786 ,  H01L21/683 ,  H01L21/84 ,  H01L23/50 ,  H01L23/528 ,  H01L27/12 ,  H01L21/8238

Abstract: Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an insulator layer on the substrate, a first doped layer on the insulator layer, at least one fin structure in contact with the doped layer, a dielectric layer surrounding a portion of the fin structure, a gate layer on the dielectric layer, a second doped layer in contact with the fin structure, a first contact area in contact with the second doped layer, and at least a first interconnect in contact with the first contact area. The structure is flipped bonded to a second substrate. The first substrate and the insulator layer are removed to expose the first doped layer. A second contact area is formed in contact with the first doped layer. At least a second interconnect is formed in contact with the second contact area.

公开(公告)号：US11056537B2

公开(公告)日：2021-07-06

申请号：US16366309

申请日：2019-03-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xin Miao ,  Richard A. Conti ,  Ruilong Xie ,  Kangguo Cheng

IPC: H01L21/28 ,  H01L27/24 ,  H01L45/00 ,  H01L21/285 ,  H01L29/66 ,  H01L29/45 ,  H01L21/768

Abstract: A middle-of-line (MOL) structure is provided and includes device and resistive memory (RM) regions. The device region includes trench silicide (TS) metallization, a first interlayer dielectric (ILD) portion and a first dielectric cap portion disposed over the TS metallization and the first ILD portion. The RM region includes a second dielectric cap portion, a second ILD portion and an RM resistor interposed between the second dielectric cap portion and the second ILD portion.

公开(公告)号：US11049935B2

公开(公告)日：2021-06-29

申请号：US16662322

申请日：2019-10-24

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Chen Zhang ,  Wenyu Xu ,  Xin Miao

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/302 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/78 ,  H01L29/41 ,  H01L29/06 ,  H01L21/336 ,  H01L29/51

Abstract: Methods are provided to construct field-effect transistors comprising low-resistance metallic gate structures. A field-effect transistor includes a nanosheet stack and a metal gate which covers a gate region of the nanosheet stack. The nanosheet stack includes nanosheet channel layers and an etch stop layer disposed above an upper nanosheet channel layer. The metal gate includes a work function metal which encapsulates the nanosheet channel layers, and a gate electrode disposed above and in contact with the work function metal. An upper surface of the work function metal is recessed to be substantially coplanar with the etch stop layer. The gate electrode has a resistivity which is less than a resistivity of the work function metal. The etch stop layer protects the portion of the work function metal disposed between the etch stop layer and the upper nanosheet channel layer from being etched when recessing the work function metal.

公开(公告)号：US20210184002A1

公开(公告)日：2021-06-17

申请号：US16717204

申请日：2019-12-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Heng Wu ,  Chen Zhang ,  Kangguo Cheng ,  Xin Miao ,  Lan Yu

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/786

Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.