公开(公告)号：US20070069282A1

公开(公告)日：2007-03-29

申请号：US11559758

申请日：2006-11-14

申请人： Hyung Kwon ,  Soon-Moon Jung

发明人： Hyung Kwon ,  Soon-Moon Jung

IPC分类号： H01L29/788 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  Y10S438/981

摘要： Semiconductor devices include a first gate pattern on a first active area of a semiconductor substrate. The first gate pattern has a top width that is substantially the same as or less than a bottom width of the first gate pattern. A second gate pattern is provided on a second active area of the semiconductor substrate. The second gate pattern has a top width that is wider than a bottom width of the second gate pattern. Semiconductor device are fabricated by forming a first gate pattern on a first gate insulation layer formed on a first active region of a semiconductor substrate. A mask insulation layer is formed on the semiconductor substrate that includes the first gate pattern. First and second gate openings respectively exposing second and third active regions of the semiconductor substrate are formed by patterning the mask insulation layer. Second and third gate insulation layers respectively are formed on second and third active regions exposed in the first and second gate openings. Second and third gate patterns are formed in the first and second gate openings respectively and the mask insulation layer is removed.

摘要翻译： 半导体器件包括在半导体衬底的第一有源区上的第一栅极图案。 第一栅极图案的顶部宽度基本上等于或小于第一栅极图案的底部宽度。 第二栅极图案设置在半导体衬底的第二有源区上。 第二栅极图案具有比第二栅极图案的底部宽度宽的顶部宽度。 通过在形成在半导体衬底的第一有源区上的第一栅极绝缘层上形成第一栅极图案来制造半导体器件。 在包括第一栅极图案的半导体基板上形成掩模绝缘层。 通过图案化掩模绝缘层来形成分别暴露半导体衬底的第二和第三有源区的第一和第二栅极开口。 第二和第三栅极绝缘层分别形成在暴露在第一和第二栅极开口中的第二和第三有源区上。 分别在第一和第二栅极开口中形成第二和第三栅极图案，并且去除掩模绝缘层。

公开(公告)号：US20070047371A1

公开(公告)日：2007-03-01

申请号：US11502397

申请日：2006-08-11

申请人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

发明人： Han-Byung Park ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： G11C8/00

CPC分类号： G11C11/412 ,  G11C11/413 ,  Y10S257/903

摘要： Example embodiments relate to a semiconductor device and a method of fabricating the same. The device may include a semiconductor substrate including a peripheral region and a cell array region, wherein the substrate in the cell array region may be recessed lower than the peripheral region, a plurality of cell transistor layers stacked in the cell array region, and a plurality of peripheral circuit transistors formed in the peripheral region. The cell transistor layers may be formed in the cell array region at a lower level than the peripheral region.

摘要翻译： 示例性实施例涉及半导体器件及其制造方法。 该器件可以包括包括外围区域和单元阵列区域的半导体衬底，其中，单元阵列区域中的衬底可以比周边区域低的凹槽，堆叠在单元阵列区域中的多个单元晶体管层，以及多个单元阵列区域 形成在外围区域的外围电路晶体管。 单元晶体管层可以形成在比周边区域更低的电池阵列区域中。

公开(公告)号：US06806180B2

公开(公告)日：2004-10-19

申请号：US10426266

申请日：2003-04-30

申请人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

发明人： Won-Seok Cho ,  Soon-Moon Jung ,  Sung-Bong Kim ,  Hyung-Shin Kwon

IPC分类号： H01L214763

CPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/76802 ,  H01L21/76895 ,  H01L27/1104

摘要： An interconnection structure is provided by foiling a first damascene interconnect structure that directly connects a first active area in a substrate, a first conductive line on the substrate and/or a first electrode on the substrate with a second active area in the substrate, a second conductive line on the substrate and/or a second electrode on the substrate. A second damascene interconnect structure may directly connect the first active area, the first conductive line and/or the first electrode to the second active area, the second conductive line and/or the second electrode. The first active area, the first conductive line and/or the first electrode connected to the second active area, the second conductive line and/or the second electrode by the first damascene interconnect structure may be different from the first active area, the first conductive line and/or the first electrode and the second active area, the second conductive line and/or the second electrode connected by the second damascene interconnect structure.

摘要翻译： 通过形成第一镶嵌互连结构来提供互连结构，所述第一镶嵌互连结构直接连接衬底中的第一有源区，衬底上的第一导电线和/或衬底上的第一电极，在衬底中具有第二有源区，第二 导电线和/或基板上的第二电极。 第二镶嵌互连结构可以将第一有源区，第一导线和/或第一电极直接连接到第二有源区，第二导线和/或第二电极。 第一有源区域，第一导电线路和/或连接到第二有源区域的第一电极，第一导电线路和/或第二电极通过第一镶嵌互连结构可以不同于第一有源区域，第一导电 线路和/或第一电极和第二有源区域，第二导电线路和/或第二电极通过第二镶嵌互连结构连接。

公开(公告)号：US06288926B1

公开(公告)日：2001-09-11

申请号：US09535871

申请日：2000-03-27

申请人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

发明人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C11/412

摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

摘要翻译： 公开了一种半导体存储器件。 该装置由多条字线组成; 垂直于字线布置的多个位线。 此外，多个电源电压线沿与位线相同的方向延伸。 此外，多个第一接地电压线被布置在与位线相同的方向上。 此外，多个第二接地电压线布置在与字线相同的方向上。 多个存储单元分别连接在一条字线和一条位线之间。 这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止 装置。

公开(公告)号：US5843811A

公开(公告)日：1998-12-01

申请号：US711126

申请日：1996-09-09

申请人： Rajiv K. Singh ,  Rolf E. Hummel ,  Soon-Moon Jung

发明人： Rajiv K. Singh ,  Rolf E. Hummel ,  Soon-Moon Jung

IPC分类号： H01L21/20 ,  H01L21/00

CPC分类号： H01L21/2022

摘要： A method of forming a crystalline thin film from an amorphous semiconductor thin film such as amorphous silicon, by providing a generally planar nucleation inducing member, such as a crystalline silicon wafer, having a number of micro-scale surface contact points and with a hardness equal to or greater than the hardness of the amorphous semiconductor thin film, contacting under pressure the surface contact points of the nucleation inducing member with the exposed surface of the amorphous thin film to form an assembly, annealing the assembly at between 300 to 700 degrees C. for 1 to 24 hours to crystallize the amorphous thin film, and removing the nucleation inducing member.

摘要翻译： 通过提供具有多个微尺度表面接触点和硬度相等的大致平面的成核诱导构件（例如晶体硅晶片），从诸如非晶硅的非晶半导体薄膜形成晶体薄膜的方法 达到或大于非晶半导体薄膜的硬度，在加压下与成核诱导构件的表面接触点与非晶薄膜的暴露表面接触以形成组件，在300-700℃之间退火组件 使无定形薄膜结晶1〜24小时，除去成核诱导部件。

公开(公告)号：US20090294863A1

公开(公告)日：2009-12-03

申请号：US12537521

申请日：2009-08-07

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： H01L29/66

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US07315466B2

公开(公告)日：2008-01-01

申请号：US11191496

申请日：2005-07-28

申请人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

发明人： Gong-Heum Han ,  Hyou-Youn Nam ,  Bo-Tak Lim ,  Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116

摘要： A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

摘要翻译： 公开了一种半导体装置及其制造方法。 半导体器件包括多个反相器，包括至少一个第一上拉晶体管和第一下拉晶体管，并分别反相并输出输入信号; 以及包括至少两个第二上拉晶体管和第二下拉晶体管的多个NAND门，并且如果至少两个输入信号中的至少一个分别具有低电平，则产生具有高电平的输出信号，其中at 至少一个第一上拉晶体管和第一下拉晶体管和至少两个第二上拉晶体管和第二下拉晶体管堆叠并布置在至少两层上。

公开(公告)号：US20060270138A1

公开(公告)日：2006-11-30

申请号：US11499946

申请日：2006-08-07

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L21/8238

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US07141851B2

公开(公告)日：2006-11-28

申请号：US10922344

申请日：2004-08-20

申请人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

发明人： Young-Chul Jang ,  Sung-Bong Kim ,  Hoon Lim ,  Soon-Moon Jung

IPC分类号： H01L29/78

CPC分类号： H01L29/66621 ,  H01L29/66553

摘要： A transistor includes a substrate and a device isolation layer that is formed on the substrate to define an active region. A gate pattern crosses over the active region. A gate insulation layer is interposed between the gate pattern and the active region. Source and drain regions are formed in the active region adjacent to respective sides of the gate pattern. A channel region is disposed in the active region between the source and drain regions. The channel region includes a recessed portion.

摘要翻译： 晶体管包括衬底和器件隔离层，其形成在衬底上以限定有源区。 栅极模式跨越有源区域。 栅极绝缘层插入在栅极图案和有源区域之间。 源极和漏极区域形成在与栅极图案的相应侧面相邻的有源区域中。 沟道区设置在源区和漏区之间的有源区中。 通道区域包括凹部。

公开(公告)号：US20050106838A1

公开(公告)日：2005-05-19

申请号：US10967374

申请日：2004-10-18

申请人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

发明人： Hoon Lim ,  Soon-Moon Jung ,  Won-Seok Cho

IPC分类号： H01L21/335 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/823481 ,  H01L21/823418

摘要： Semiconductor devices and methods of fabricating semiconductor devices that include a substrate and a device isolation layer in the substrate that defines an active region of the substrate are provided. The device isolation layer has a vertically protruding portion having a sidewall that extends vertically beyond a surface of the substrate. An epitaxial layer is provided on the surface of the substrate in the active region and extends onto the device isolation layer. The epitaxial layer is spaced apart from the sidewall of the vertically protruding portion of the device isolation layer. A gate pattern is provided on the epitaxial layer and source/drain regions are provided in the epitaxial layer at opposite sides of the gate pattern.

摘要翻译： 提供制造半导体器件的半导体器件和方法，其包括限定衬底的有源区的衬底中的衬底和器件隔离层。 器件隔离层具有垂直突出部分，其具有垂直延伸超出衬底表面的侧壁。 在有源区中的衬底的表面上提供外延层并延伸到器件隔离层上。 外延层与器件隔离层的垂直突出部分的侧壁间隔开。 在外延层上提供栅极图案，并且在栅极图案的相对侧的外延层中设置源极/漏极区域。