公开(公告)号：US5942911A

公开(公告)日：1999-08-24

申请号：US123149

申请日：1998-07-27

申请人： Franco Motika ,  Paul Motika ,  Phil Nigh

发明人： Franco Motika ,  Paul Motika ,  Phil Nigh

IPC分类号： G01R31/28 ,  G01R31/312 ,  G01R31/26

CPC分类号： G01R31/312 ,  G01R31/2851

摘要： The manufacture of an integrated circuit chip includes testing the integrated circuit while an external electric field is applied to the integrated circuit to facilitate detection of open circuit type defects. The electric field may be provided by applying a high potential to a plate parallel to a plane of the integrated circuit or by applying a high potential to a probe and moving the probe across the surface of the integrated circuit chip to obtain information regarding the location of the defect. Use of a probe type electric field generator allows the approximate position of the defect to be determined. The invention enhances current testing and diagnostics methods for wafers, chips, and integrated circuit packages by allowing detection of floating net defects during other conventional tests.

摘要翻译： 集成电路芯片的制造包括测试集成电路，同时将外部电场施加到集成电路以便于检测开路型缺陷。 可以通过向平行于集成电路的平面的板施加高电位或者通过向探针施加高电位并将探针移动跨越集成电路芯片的表面来获得有关位置的信息来提供电场 缺陷。 使用探针型电场发生器可以确定缺陷的大致位置。 本发明通过在其他常规测试期间允许检测浮动净缺陷来增强晶片，芯片和集成电路封装的电流测试和诊断方法。

公开(公告)号：US4745355A

公开(公告)日：1988-05-17

申请号：US48178

申请日：1987-05-11

申请人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

发明人： Edward B. Eichelberger ,  Roger N. Langmaid ,  Eric Lindbloom ,  Franco Motika ,  John L. Sinchak ,  John A. Waicukauski

IPC分类号： G01R31/3185 ,  G06F11/277 ,  G01R31/28

CPC分类号： G01R31/318566 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/31908 ,  G06F11/277 ,  G06F2201/83

摘要： A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

摘要翻译： 一种用于测试非常大规模的集成电路装置，特别是水平敏感扫描设计（LSSD）装置的方法和装置，通过将不同配置的伪随机图案序列并行地应用于被测设备的每个输入端，收集 并行地输出来自每个输出端子的响应，组合这些输出以获得作为并行输出的所有序列的预定函数的签名，并将测试签名与通过计算机模拟获得的已知的良好签名进行比较。 输入测试刺激以预定方式进一步改变为待测试设备的结构的函数，以单独加权输入以有利于更多或更少的二进制或零。

公开(公告)号：US08843797B2

公开(公告)日：2014-09-23

申请号：US13534444

申请日：2012-06-27

申请人： Franco Motika ,  Raymond J. Kurtulik ,  John D. Parker

发明人： Franco Motika ,  Raymond J. Kurtulik ,  John D. Parker

IPC分类号： G01R31/28 ,  G06F11/27 ,  G01R31/3193

CPC分类号： G06F11/27 ,  G01R31/318547 ,  G01R31/3193

摘要： A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the LFSR and one or more save and restore registers; initializing a MISR and running test loops. Upon reaching a predetermined number of test loops, moving a signature of the MISR to a shadow register; then, performing a signature stability test by loading the initial seed to the LFSR; executing the predetermined number of BIST test loops, and comparing a resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register, wherein unloading is performed by way of serial MISR unloads and single bit XORs.

摘要翻译： 一种用于在测试VLSI芯片时检测不稳定签名的方法，包括向LFSR添加一个或多个保存和恢复寄存器以存储由0和1组成的初始种子; 将初始种子加载到LFSR和一个或多个保存和恢复寄存器; 初始化MISR并运行测试循环。 当达到预定数量的测试循环时，将MISR的签名移动到影子寄存器; 然后，通过将初始种子加载到LFSR来执行签名稳定性测试; 执行预定数量的BIST测试循环，并且将差异的结果MISR签名与存储在MISR保存和恢复寄存器中的先前签名进行比较，其中通过串行MISR卸载和单位异或来执行卸载。

公开(公告)号：US07971176B2

公开(公告)日：2011-06-28

申请号：US12050207

申请日：2008-03-18

申请人： Rao H. Desineni ,  Maroun Kassab ,  Franco Motika ,  Leah Marie Pfeifer Pastel

发明人： Rao H. Desineni ,  Maroun Kassab ,  Franco Motika ,  Leah Marie Pfeifer Pastel

IPC分类号： G06F17/50 ,  G06F11/22 ,  G06F19/00

CPC分类号： G01R31/31835

摘要： A method of testing an integrated circuit. The method includes selecting a set of physical features of nets and devices of the integrated circuit, the integrated circuit having pattern input points and pattern observation points connected by the nets, each of the nets defined by an input point and all fan out paths to (i) input points of other nets of the nets or (ii) to the pattern observation points; selecting a measurement unit for each feature of the set of features; assigning a weight to each segment of each fan out path based on a number of the measurement units of the feature in each segment of each fan out path of each of the nets; and generating a set of test patterns optimized for test-coverage and cost based on the weights assigned to each segment of each of the nets of the integrated circuit.

摘要翻译： 一种集成电路测试方法。 该方法包括选择集成电路的网络和设备的一组物理特征，集成电路具有由网络连接的模式输入点和模式观察点，每个网络由输入点定义，并且所有扇出路径到（ i）网的其他网的输入点或（ii）到模式观察点; 为特征集合中的每个特征选择测量单元; 基于每个网络的每个扇出路径的每个段中的特征的测量单元的数量，为每个扇出路径的每个段分配权重; 以及基于分配给集成电路的每个网络的每个段的权重，生成针对测试覆盖和成本优化的一组测试模式。

公开(公告)号：US20080211530A1

公开(公告)日：2008-09-04

申请号：US12103906

申请日：2008-04-16

申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

公开(公告)号：US20080172576A1

公开(公告)日：2008-07-17

申请号：US11622055

申请日：2007-01-11

申请人： Mary P. Kusko ,  Gary W. Maier ,  Franco Motika ,  Phong T. Tran

发明人： Mary P. Kusko ,  Gary W. Maier ,  Franco Motika ,  Phong T. Tran

IPC分类号： G06F11/26

CPC分类号： G06F11/261

摘要： A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.

摘要翻译： 适用于VLSI设计的诊断过程，以解决诊断解决的准确性。 基于环境的故障数据驱动自适应测试方法，其中测试模式集合和数据收集失败，以便成功诊断分辨率。 基于环境的故障数据用于诊断仿真，以实现更准确的基于环境的故障标注。 当需要时，该过程中将包含其他信息，以进一步完善和定义模拟或标注结果。 类似地，根据需要采用自适应测试模式生成方法来提高诊断分辨率。

公开(公告)号：US07400162B2

公开(公告)日：2008-07-15

申请号：US10539247

申请日：2003-02-20

申请人： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

发明人： Anne Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/2856 ,  G01R31/3004 ,  G01R31/3008

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

摘要翻译： 测试半导体电路（10）的方法，包括在测试期间测试电路和修改电路的阱偏压（14,18）。 该方法通过在测试过程中改善阱偏差来提高基于电压和IDDQ测试和诊断的分辨率。 此外，这些方法在应力测试期间提供更有效的应力。 该方法适用于半导体阱（阱和/或衬底）与芯片VDD和GND分开接线的IC，允许在测试期间外部控制（40）阱电位。 通常，这些方法依靠使用阱偏置来改变晶体管阈值电压。

公开(公告)号：US20080098268A1

公开(公告)日：2008-04-24

申请号：US11933385

申请日：2007-10-31

申请人： Leendert Huisman ,  William Huott ,  Franco Motika ,  Leah Pfeifer Pastel

发明人： Leendert Huisman ,  William Huott ,  Franco Motika ,  Leah Pfeifer Pastel

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/318594 ,  G01R31/31922 ,  G01R31/31937

摘要： In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

摘要翻译： 在一个方面，测试了通过使用时钟门控或信号门控被划分成段的电子设备。 识别出作为故障来源的细分之一。 将诊断程序应用于识别的段以确定故障的原因。

公开(公告)号：US07313744B2

公开(公告)日：2007-12-25

申请号：US10708380

申请日：2004-02-27

申请人： Leendert M. Huisman ,  William V. Huott ,  Maroun Kassab ,  Franco Motika

发明人： Leendert M. Huisman ,  William V. Huott ,  Maroun Kassab ,  Franco Motika

IPC分类号： G01R31/28

CPC分类号： G01R31/318533

摘要： Systems, methods and apparatus are provided for isolating a defect in a scan chain. The invention includes modifying a first test mode of a plurality of latches included in a scan chain, operating the latches in the modified first test mode, and operating the plurality of latches included in the scan chain in a second test mode. A portion of the scan chain adjacent and following a stuck-@-0 or stuck-@-1 fault in the scan chain may store and/or output a value complementary to the value on the output of the previous portion of the scan chain due to the fault. Such values may be unloaded from the scan chain and used for diagnosing (e.g., isolating a defect in) the defective scan chain. Numerous other aspects are provided.

摘要翻译： 提供了用于隔离扫描链中的缺陷的系统，方法和装置。 本发明包括修改包括在扫描链中的多个锁存器的第一测试模式，在修改的第一测试模式下操作锁存器，以及在第二测试模式下操作包括在扫描链中的多个锁存器。 扫描链中与扫描链相邻并跟随卡纸 - @ - 0或卡住 - - - 1故障的部分扫描链可以存储和/或输出与扫描链的先前部分的输出值相匹配的值， 到了错误。 这些值可以从扫描链中卸载并用于诊断（例如，分离缺陷）缺陷扫描链。 提供了许多其他方面。

公开(公告)号：US20060237529A1

公开(公告)日：2006-10-26

申请号：US11427148

申请日：2006-06-28

申请人： Edward Kelley ,  Franco Motika ,  Kim Ruffing

发明人： Edward Kelley ,  Franco Motika ,  Kim Ruffing

IPC分类号： G06K5/00

CPC分类号： G07F7/1008 ,  G06Q20/341 ,  G06Q20/382 ,  G07F7/0886

摘要： A secure card adapter provides for writing of highly secure, single transaction information on a machine-readable medium of a card structure in accordance with a format that may be downloaded from an external data source. The card structure may be, for example, an existing access authorization card or an existing credit card containing account-specific information which can be read and stored in memory of the secure card adapter. Once such account-specific information is read from an existing access authorization or credit card, secure transaction information can be written, together with the account specific information in accordance with the downloaded format information on another card structure to provide a universal access authorization and/or credit card. Thus the secure card adapter provides an enhanced degree of security through an existing or transitional communication infrastructure.

摘要翻译： 安全卡适配器提供根据可从外部数据源下载的格式在卡结构的机器可读介质上写入高度安全的单个交易信息。 卡结构可以是例如现有的访问授权卡或包含可被读取并存储在安全卡适配器的存储器中的特定于特定信息的现有信用卡。 一旦从现有的访问授权或信用卡读取这样的特定于特定信息的信息，可以根据下载的关于另一个卡结构的格式信息，将帐户特定信息与安全交易信息一起写入以提供通用访问授权和/或 信用卡。 因此，安全卡适配器通过现有或过渡的通信基础设施提供增强的安全性。