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192 条记录 (耗时 0.032 秒)

    Multi-Bit Flash Memory Devices and Methods of Programming and Erasing the Same
    91.
    发明申请
    Multi-Bit Flash Memory Devices and Methods of Programming and Erasing the Same 有权
    多位闪存设备及其编程和擦除方法

    公开(公告)号：US20100020601A1

    公开(公告)日：2010-01-28

    申请号：US12471729

    申请日：2009-05-26

    申请人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

    发明人： Se-Hoon Lee ,  Choong-Ho Lee ,  Jung-Dal Choi

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5628 ,  G11C2211/5641

    摘要： A non-volatile memory device includes an array of non-volatile memory cells configured to support single bit and multi-bit programming states. A control circuit is provided, which is configured to program a first page of non-volatile memory cells in the array as M-bit cells during a first programming operation and further configured to program the first page of non-volatile memory cells as N-bit cells during a second programming operation. The first and second programming operations are separated in time by at least one operation to erase the first page of non-volatile memory cells. M and N are unequal integers greater than zero.

    摘要翻译： 非易失性存储器件包括被配置为支持单位和多位编程状态的非易失性存储器单元的阵列。 提供了一种控制电路，其被配置为在第一编程操作期间将阵列中的第一页非易失性存储单元编程为M位单元，并且还被配置为将第一页非易失性存储单元编程为N- 在第二次编程操作期间。 第一和第二编程操作通过至少一个擦除非易失性存储器单元的第一页的操作在时间上被分离。 M和N是不等于零的整数。

    Nonvolatile Memory Device
    92.
    发明申请
    Nonvolatile Memory Device 有权
    非易失性存储器件

    公开(公告)号：US20090315094A1

    公开(公告)日：2009-12-24

    申请号：US12437773

    申请日：2009-05-08

    申请人： Jong-Ho Lim ,  Choong-Ho Lee ,  Hye-Jin Cho

    发明人： Jong-Ho Lim ,  Choong-Ho Lee ,  Hye-Jin Cho

    IPC分类号： H01L29/788

    CPC分类号： H01L27/11551

    摘要： Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.

    摘要翻译： 具有三维结构的非易失性存储装置。 非易失性存储器件包括多个堆叠的半导体层和形成在多个半导体层中的每一个上并且串联连接的多个存储单元晶体管。 配置在不同的半导体层上的存储单元晶体管被串联连接以包括在多个半导体层中形成电流路径的一个单元串，串联连接到单元串的一个边缘部分的第一选择晶体管和串联连接到单元串的第二选择晶体管 单元格串的其他边缘部分。

    Non-volatile memory device and method of manufacturing the same
    93.
    发明授权
    Non-volatile memory device and method of manufacturing the same 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US07615437B2

    公开(公告)日：2009-11-10

    申请号：US12153071

    申请日：2008-05-13

    申请人： Suk-Kang Sung ,  Kyu-Charn Park ,  Choong-Ho Lee

    发明人： Suk-Kang Sung ,  Kyu-Charn Park ,  Choong-Ho Lee

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/743 ,  H01L21/28123 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： A method of manufacturing a non-volatile memory device includes sequentially depositing a first insulation layer, a charge storage layer, and a second insulation layer on a substrate, forming a first opening through the resultant structure to expose the substrate, forming second and third openings through the second insulation layer to form a second insulation layer pattern, forming a conductive layer on the second insulation layer pattern, forming a photoresist pattern structure on the conductive layer, and forming simultaneously a common source line, at least one ground selection line, at least one string selection line, and a plurality of gate structures on the substrate by etching through the photoresist pattern structure, wherein the common source line and the gate structures are formed simultaneously on a substantially same level and of substantially same components.

    摘要翻译： 一种制造非易失性存储器件的方法包括在衬底上依次沉积第一绝缘层，电荷存储层和第二绝缘层，形成通过所得结构的第一开口以露出衬底，形成第二和第三开口 通过第二绝缘层形成第二绝缘层图案，在第二绝缘层图案上形成导电层，在导电层上形成光致抗蚀剂图形结构，同时形成共同的源极线，至少一个接地选择线， 至少一个串选择线，以及通过蚀刻通过光致抗蚀剂图案结构在衬底上的多个栅极结构，其中公共源极线和栅极结构同时形成在基本相同的水平面上并且基本上相同的部件。

    Non-volatile memory device, method of manufacturing the same, and method of operating the same
    94.
    发明授权
    Non-volatile memory device, method of manufacturing the same, and method of operating the same 有权
    非易失性存储器件，其制造方法及其操作方法

    公开(公告)号：US07602633B2

    公开(公告)日：2009-10-13

    申请号：US11946737

    申请日：2007-11-28

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Kyu-Charn Park

    IPC分类号： G11C11/00

    CPC分类号： H01L29/685

    摘要： A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.

    摘要翻译： 非易失性存储器件包括衬底，电阻图案，栅极介电层，栅极电极图案，第一杂质区域和第二杂质区域。 基板有凹槽。 凹槽中填充有电阻图案。 电阻图案包括具有根据施加到其上的电压而可变的电阻的材料。 栅极电介质层形成在基板上。 栅极电极图案形成在栅极介电层上。 在衬底中形成第一和第二杂质区。 电阻图案的第一杂质区和第二杂质区接触侧表面。 此外，电阻图案，第一杂质区域和第二杂质区域限定沟道区域。 因此，非易失性存储器件可以使用电阻图案的可变电阻来存储数据，使得非易失性存储器件可以具有优异的操作特性。

    Method of forming fin field effect transistor using damascene process
    96.
    发明授权
    Method of forming fin field effect transistor using damascene process 有权
    使用镶嵌工艺形成翅片场效应晶体管的方法

    公开(公告)号：US07528022B2

    公开(公告)日：2009-05-05

    申请号：US11112818

    申请日：2005-04-21

    申请人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Dong-Gun Park ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7851 ,  H01L21/26586 ,  H01L29/66818

    摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.

    摘要翻译： 提供了一种使用镶嵌工艺形成鳍式晶体管的方法。 填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。 图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。 形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。 通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

    Non-volatile memory device and methods of forming the same
    97.
    发明授权
    Non-volatile memory device and methods of forming the same 有权
    非易失性存储器件及其形成方法

    公开(公告)号：US07465985B2

    公开(公告)日：2008-12-16

    申请号：US11580086

    申请日：2006-10-13

    申请人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    发明人： Byung-Yong Choi ,  Choong-Ho Lee ,  Dong-Gun Park

    IPC分类号： H01L21/334

    CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

    摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

    摘要翻译： 提供了一种非易失性存储器件及其形成方法。 非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案 电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和 位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

    Method of fabricating semiconductor devices having MCFET/finFET and related device
    99.
    发明申请
    Method of fabricating semiconductor devices having MCFET/finFET and related device 审中-公开
    制造具有MCFET / finFET及相关器件的半导体器件的方法

    公开(公告)号：US20070114612A1

    公开(公告)日：2007-05-24

    申请号：US11443816

    申请日：2006-05-31

    申请人： Young-Joon Ahn ,  Choong-Ho Lee ,  Hee-Soo Kang

    发明人： Young-Joon Ahn ,  Choong-Ho Lee ,  Hee-Soo Kang

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L29/7851

    摘要： In a method of fabricating a semiconductor device having both a MCFET and a finFET on a common substrate, a first hard mask pattern and a second hard mask pattern are formed on a substrate, the second hard mask pattern having a width in a horizontal direction that is less than that of the first hard mask pattern, and the second hard mask pattern being spaced apart from the first hard mask pattern. The substrate is partially removed using the first and second hard mask patterns as etch masks, and forming a preliminary multi-fin structure below the first hard mask pattern and a single fin structure below the second hard mask pattern. A concave portion is formed in the preliminary multi-fin structure to form a multi-fin structure.

    摘要翻译： 在制造在共用衬底上具有MCFET和finFET的半导体器件的方法中，在衬底上形成第一硬掩模图案和第二硬掩模图案，第二硬掩模图案在水平方向上具有宽度，即 小于第一硬掩模图案的厚度，并且第二硬掩模图案与第一硬掩模图案间隔开。 使用第一和第二硬掩模图案作为蚀刻掩模部分地去除衬底，以及在第一硬掩模图案下方形成初步的多鳍结构，以及在第二硬掩模图案下面形成单个鳍结构。 在预备的多翅片结构中形成凹部以形成多翅片结构。

    Fin FET and method of fabricating same
    100.
    发明授权
    Fin FET and method of fabricating same 有权
    翅片FET及其制造方法

    公开(公告)号：US07217623B2

    公开(公告)日：2007-05-15

    申请号：US11050915

    申请日：2005-02-04

    申请人： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

    发明人： Keun-Nam Kim ,  Hung-Mo Yang ,  Choong-Ho Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7854 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7856

    摘要： A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

    摘要翻译： 使用体硅衬底形成鳍状场效应晶体管（鳍FET），并通过在翅片有源区中形成具有预定深度的凹槽，然后通过在上部形成栅极来充分保证形成在栅极下方的顶部沟道长度 部分休息。 形成器件隔离膜以在衬底的预定区域中限定非有源区和鳍有源区。 在器件隔离膜的一部分中，形成第一凹部，并且在翅片有源区域的一部分中形成有比第一凹部浅的深度的第二凹部。 栅极绝缘层形成在第二凹部内，栅极形成在第二凹部的上部。 源极/漏极区域形成在栅电极的两侧的鳍片有源区域中。