公开(公告)号：US12073883B2

公开(公告)日：2024-08-27

申请号：US17742148

申请日：2022-05-11

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng-Hao Yeh ,  Chih-Chang Hsieh

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: A ternary content addressable memory, disposed in a stacked memory device, includes a first memory cell string and a second memory cell string. The first memory cell string is coupled between a matching line and a first source line and receives multiple first word line signals. The first memory cell string has a first memory cell string selection switch controlled by a first search signal. The second memory cell string is coupled between the matching line and a second source line and receives multiple second word line signals. The second memory cell string has a second memory cell string selection switch controlled by a second search signal.

公开(公告)号：US11894065B2

公开(公告)日：2024-02-06

申请号：US17569424

申请日：2022-01-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Tzu-Hsuan Hsu

IPC: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.

公开(公告)号：US20240028211A1

公开(公告)日：2024-01-25

申请号：US18161900

申请日：2023-01-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Teng-Hao Yeh ,  Chih-Chang Hsieh ,  Chun-Hsiung Hung ,  Yung-Chun LI

IPC: G06F3/06 ,  G11C16/28

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/28

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

公开(公告)号：US11778823B2

公开(公告)日：2023-10-03

申请号：US17125407

申请日：2020-12-17

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue ,  Guan-Ru Lee

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: The present disclosure provides a three-dimensional memory device and a method for manufacturing the same. The three-dimensional memory device includes a plurality of tiles, and each tiles includes a plurality of blocks, and each blocks includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure is disposed on the substrate and includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate, and each of the first ring-shaped channel pillars are configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.

公开(公告)号：US20230225126A1

公开(公告)日：2023-07-13

申请号：US17575418

申请日：2022-01-13

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Chia-Jung Chiu ,  Teng-Hao Yeh ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A three-dimensional AND flash memory device includes a gate stack structure, a charge storage structure, a first conductive pillar and a second conductive pillar, an insulating pillar, and a channel pillar. The gate stack structure includes gate layers and insulating layers stacked alternately with each other. The first and second conductive pillars extend through the gate stack structure. The channel pillar extends through the gate stack structure. The charge storage structure is disposed between the gate stack structure and the channel pillar. The channel pillar includes: a first part and a second part connected each other. The first part is located between the charge storage structure and the insulating pillar. The second part includes a first region electrically connected to the first conductive pillar, and a second region electrically connected to the second conductive pillar. A curvature of the first part is smaller than a curvature of the second part.

公开(公告)号：US11417683B2

公开(公告)日：2022-08-16

申请号：US17077847

申请日：2020-10-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: H01L27/11597 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11587

Abstract: Provided is a flash memory includes a gate stack structure, a channel pillar, a first conductive pillar, a second conductive pillar, and a gate dielectric layer. The gate stack structure includes a plurality of gate layers electrically insulated from each other. Each gate layer includes a ferroelectric portion disposed between a sidewall of a first portion and a sidewall of a second gate portion. A thickness of the second gate portion is smaller than a thickness of the first gate portion. A channel pillar penetrates the gate stack structure. The first and second conductive pillars are disposed in the channel pillar. The first and second conductive pillars are separated from each other, and are each connected to the channel pillar. The gate dielectric layer is disposed between another sidewall of the first gate portion and the channel pillar.

公开(公告)号：US20220157848A1

公开(公告)日：2022-05-19

申请号：US17185275

申请日：2021-02-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Guan-Ru Lee

IPC: H01L27/11582 ,  H01L27/11565

Abstract: Provided is a memory device including a substrate, a stack structure, a polysilicon layer, a vertical channel structure, and a charge storage structure. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The polysilicon layer is disposed between the substrate and the stack structure. The vertical channel structure penetrates through the stack structure and the polysilicon layer. The charge storage structure is at least disposed between the vertical channel structure and the plurality of conductive layers.

公开(公告)号：US11081182B2

公开(公告)日：2021-08-03

申请号：US16667536

申请日：2019-10-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04

Abstract: An integrated circuit and a computing method thereof are provided. The integrated circuit includes a memory array, word lines, bit lines and a page buffer. The memory array includes memory cells, each configured to be programmed with a weight. The word lines respectively connect a row of the memory cells. The bit lines are respectively connected with a column of the memory cells that are connected in series. More than one of the bit lines in a block of the memory array or more than one of the word lines in multiple blocks of the memory array are configured to receive input voltages. The memory cells receiving the input voltages are configured to multiply the weights stored therein and the received input voltages. The page buffer is coupled to the memory array, and configured to sense products of the weights and the input voltages.

公开(公告)号：US20210193677A1

公开(公告)日：2021-06-24

申请号：US16923144

申请日：2020-07-08

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen CHEN

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a stack formed on a substrate and memory strings penetrating the stack along a first direction. The stack includes conductive layers and insulating layers that alternately stacked. Each of the memory strings includes a channel layer, a memory structure, a first conductive pillar and a second conductive pillar. The channel layer, the first conductive pillar and the second conductive pillar extend along a first direction. The memory structure is disposed between the stack and the channel layer. The first conductive pillar and the second conductive pillar are electrically isolated from each other, and are respectively coupled to a first location and a second location of the channel layer. The first location is opposite to the second location. The first location is surrounded by the memory structure, and the second location is exposed from the memory structure.

公开(公告)号：US10910399B2

公开(公告)日：2021-02-02

申请号：US16353028

申请日：2019-03-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L21/311 ,  H01L29/06 ,  H01L21/762 ,  H01L21/28

Abstract: A three-dimensional memory device includes a substrate, a plurality of conductive layers and insulating layers, a memory layer stack, an isolation portion, a second hole and a dielectric filler. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The multi-layer stacked structure includes multiple first holes, and each first hole passing through the conductive layers and the insulating layers. The memory layer stack has a first string portion, a second string portion and a bottom string portion connected between the first and second string portions. The isolation portion is embedded among the first, second and bottom string portions of each of the memory layer stacks in the first holes. The dielectric filler is located on the isolation portion and has side protrusions in contact with the conductive layers.