公开(公告)号：US11561892B2

公开(公告)日：2023-01-24

申请号：US17118152

申请日：2020-12-10

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/02 ,  G11C16/10 ,  G11C11/16

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window.

公开(公告)号：US20220308955A1

公开(公告)日：2022-09-29

申请号：US17725226

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Qing Liang

IPC: G06F11/07

Abstract: Methods, systems, and devices for memory data correction using multiple error control operations are described. A single command may be received to correct an error detected in data stored by a memory array. A first error control operation and a second error control operation may be implemented based on the single command. The first error control operation may be performed on the data stored by the memory array using one or more different reference voltages to read the data. The error may be determined to remain in the data after performing the first error control operation. The second error control operation may then be performed on the data stored by the memory array. The second error control operation may use one or more voltage distributions associated with the memory cells of the memory array.

公开(公告)号：US20220300374A1

公开(公告)日：2022-09-22

申请号：US17648395

申请日：2022-01-19

Applicant: Micron Technology, Inc.

Inventor： Chun Sum Yeung ,  Jonathan S. Parry ,  Deping He ,  Xiangang Luo ,  Reshmi Basu

IPC: G06F11/10

Abstract: Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.

公开(公告)号：US20220075722A1

公开(公告)日：2022-03-10

申请号：US17527776

申请日：2021-11-16

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He ,  David Aaron Palmer

IPC: G06F12/02 ,  G11C11/16 ,  G11C16/10

Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to an estimated device age are discussed. An exemplary memory device includes a memory controller to track an actual device age, determine a device wear metric using a physical write count and total writes over an expected lifetime of the memory device, estimate a wear-indicated device age, and adjust an amount of memory space to be freed by a GC operation according to the wear-indicated device age relative to the actual device age. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the wear-indicated device age relative to the actual device age.

公开(公告)号：US11194643B1

公开(公告)日：2021-12-07

申请号：US16891615

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

IPC: G06F11/07 ,  G06F11/30

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

公开(公告)号：US11158387B1

公开(公告)日：2021-10-26

申请号：US16941894

申请日：2020-07-29

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jingyuan Miao

IPC: G11C11/34 ,  G11C16/26 ,  G11C11/56

Abstract: Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.

公开(公告)号：US10956065B2

公开(公告)日：2021-03-23

申请号：US16512256

申请日：2019-07-15

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Deping He

IPC: G06F3/06 ,  G11C29/52 ,  G06F9/4401 ,  G06F11/10

Abstract: Several embodiments of memory devices and related methods for initializing such memory devices based on initialization information stored in NAND-based memory media. In one embodiment, a memory device can include a controller operably coupled to the memory media. The controller is configured to determine whether the initialization information stored at a region of the memory media is valid, initialize the memory device based at least in part on the initialization information when valid, and invalidate the initialization information stored at the region of the memory media by writing to the region of the memory media without first erasing the region of the memory media.

公开(公告)号：US20190324876A1

公开(公告)日：2019-10-24

申请号：US16504067

申请日：2019-07-05

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Allen Thomson

IPC: G06F11/20 ,  G11C29/00 ,  G11C16/34 ,  G06F11/10

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US10387281B2

公开(公告)日：2019-08-20

申请号：US15690903

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Giuseppe Cariello ,  Deping He ,  Scott Anthony Stoller ,  Devin Batutis ,  Preston Thomson

IPC: G06F11/20

Abstract: Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.

公开(公告)号：US12292831B2

公开(公告)日：2025-05-06

申请号：US18616993

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  David Aaron Palmer

IPC: G06F12/00 ,  G06F11/10 ,  G06F11/30 ,  G06F12/0811 ,  G06F12/0882 ,  G06F12/0891

Abstract: Methods, systems, and devices for enhanced data reliability in multi-level memory cells are described. For a write operation, a host device may identify a first set of data to be stored by a set of memory cells at a memory device. Based on a quantity of bits within the first set of data being less than a storage capacity of the set of memory cells, the host device may generate a second set of data and transmit a write command including the first and second sets of data to the memory device. For a read operation, the host device may receive a first set of data from the memory device in response to transmitting a read command. The memory device may extract a second set of data from the first set of data and validate a portion of the first set of data using the second set of data.