公开(公告)号：US20240330667A1

公开(公告)日：2024-10-03

申请号：US18738644

申请日：2024-06-10

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  William A. Melton

IPC: G06N3/063 ,  G06F3/06 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

CPC classification number: G06N3/063 ,  G06F3/0604 ,  G06F3/0661 ,  G06F3/0673 ,  G06N3/04 ,  G11C7/06 ,  G11C8/08 ,  G11C11/54 ,  H03M1/46

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Bits of a first number may be stored on a number of memory elements, wherein each memory element of the number of memory elements intersects a digit line and an access line of a number of access lines. A number of signals corresponding to bits of a second number may be driven on the number of access lines to generate a number of output signals. A value equal to a product of the first number and the second number may be generated based on the number of output signals.

公开(公告)号：US20240273349A1

公开(公告)日：2024-08-15

申请号：US18642669

申请日：2024-04-22

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06N3/049 ,  G06N3/084 ,  G06N5/046 ,  G11C11/4063 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US20240233869A9

公开(公告)日：2024-07-11

申请号：US18049498

申请日：2022-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G06F16/903

CPC classification number: G16B30/10 ,  G06F16/90339

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US20240232601A1

公开(公告)日：2024-07-11

申请号：US18582467

申请日：2024-02-20

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/063 ,  G06F12/06 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06F12/0646 ,  G06N3/04 ,  G06F2212/1008

Abstract: Methods, apparatuses, and systems for in- or near-memory processing are described. Spiking events in a spiking neural network may be processed via a memory system. A memory system may store a group of destination neurons, and at each time interval in a series of time intervals of a spiking neural network (SNN), pass through a group of pre-synaptic spike events from respective source neurons, wherein the group of pre-synaptic spike events are subsequently stored in memory.

公开(公告)号：US12021547B2

公开(公告)日：2024-06-25

申请号：US17677593

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10 ,  G11C15/04 ,  H03M13/15 ,  H03M13/43

CPC classification number: H03M13/1575 ,  G06F11/1068 ,  G11C15/04 ,  H03M13/43

Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.

公开(公告)号：US20240152292A1

公开(公告)日：2024-05-09

申请号：US18415285

申请日：2024-01-17

Applicant: Micron Technology, Inc.

Inventor： Sean S. Eilert ,  Kenneth M. Curewitz ,  Helena Caminal ,  Ameen D. Akel

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for redundant computing across planes are described. A device may perform a computational operation on first data that is stored in a first plane that includes content-addressable memory cells. The first data may be representative of a set of contiguous bits of a vector. The device may perform, concurrent with performing the computational operation on the first data, the computational operation on second data that is stored in a second plane. The second data may be representative of the set of contiguous bits of the vector. The device may read from the first plane and write to the second plane, third data representative of a result of the computational operation on the first data.

公开(公告)号：US20240136015A1

公开(公告)日：2024-04-25

申请号：US18049498

申请日：2022-10-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G16B30/10 ,  G06F16/903

CPC classification number: G16B30/10 ,  G06F16/90339

Abstract: Associative processing memory (APM) may be used to align reads to a reference sequence. The APM may store shifted permutations and/or other permutations of the reference sequence. A read may be compared to some or all of the permutations of the reference sequence and the APM may provide an output for each comparison. In some examples, the APM may compare the read to many permutations of the reference sequence to the read in parallel. Inferences may be made based on the comparisons between the read and the portions and/or permutations of a reference sequence. Based on the inferences, a candidate alignment location in the reference sequence for a read to be determined.

公开(公告)号：US11869589B2

公开(公告)日：2024-01-09

申请号：US17188843

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Sean S. Eilert

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: An apparatus (e.g., a content addressable memory system) can have a controller; a first content addressable memory coupled to the controller and a second content addressable memory coupled to the controller. The controller can be configured to cause the first content addressable memory to compare input data to first data stored in the first content addressable memory and cause the second content addressable memory to compare the input data to second data stored in the second content addressable memory such the input data is compared to the first and second data concurrently and replace a result of the comparison of the input data to the first data with a result of the comparison of the input data to the second data in response to determining that the first data is invalid and that the second data corresponds to the first data.

公开(公告)号：US11868268B2

公开(公告)日：2024-01-09

申请号：US17665823

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Sean S. Eilert ,  Hongyu Wang ,  Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Justin M. Eno ,  Shivam Swami

IPC: G06F12/10 ,  G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027 ,  G06F2212/657 ,  G06F2212/68

Abstract: A computer system includes physical memory devices of different types that store randomly-accessible data in a main memory of the computer system. In one approach, data is stored in memory at one or more logical addresses allocated to an application by an operating system. The data is physically stored in a first memory device of a first memory type (e.g., NVRAM). The operating system determines an access pattern for the stored data. In response to determining the access pattern, the data is moved from the first memory device to a second memory device of a different memory type (e.g., DRAM).

公开(公告)号：US11853230B2

公开(公告)日：2023-12-26

申请号：US17329989

申请日：2021-05-25

Applicant: Micron Technology, Inc.

Inventor： Donald M. Morgan ,  Sean S. Eilert ,  Bryce D. Cook

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0238 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7208 ,  G06F2212/7211

Abstract: Methods, systems, and devices for address obfuscation for memory are described. A mapping function may map a logical address of data to a physical address of a memory cell. The mapping function may be implemented with a mapping component that includes mapping subcomponents. Each mapping subcomponent may be independently configurable to implement a logic function for determining a bit of the physical address. The mapping function may vary across memory devices or aspects of memory device, and in some cases may vary over time.