公开(公告)号：US07863680B2

公开(公告)日：2011-01-04

申请号：US12167437

申请日：2008-07-03

申请人： Markus Zundel ,  Rudolf Zelsacher ,  Franz Hirler ,  Dietmar Kotz ,  Hermann Peri ,  Armin Willmeroth

发明人： Markus Zundel ,  Rudolf Zelsacher ,  Franz Hirler ,  Dietmar Kotz ,  Hermann Peri ,  Armin Willmeroth

IPC分类号： H01L27/088

CPC分类号： H01L29/7813 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7811

摘要： A semiconductor component includes a surface region. A modified doping region is provided in the edge region of the cell array. In the surface region or modified doping region the doping concentration is lowered and/or in the surface region or modified doping region the conductivity type is formed such that it is opposite to the conductivity type of the actual semiconductor material region, or in which a field plate region is provided.

摘要翻译： 半导体部件包括表面区域。 在单元阵列的边缘区域中提供修改的掺杂区域。 在表面区域或改性掺杂区域中，掺杂浓度降低和/或在表面区域或修饰掺杂区域中形成导电类型，使其与实际半导体材料区域的导电类型相反，或者其中场 板区域。

公开(公告)号：US07851349B2

公开(公告)日：2010-12-14

申请号：US11527743

申请日：2006-09-26

申请人： Walter Rieger ,  Paul Ganitzer ,  Oliver Haeberlen ,  Franz Hirler ,  Markus Zundel ,  Rudolf Zelsacher ,  Erwin Bacher

发明人： Walter Rieger ,  Paul Ganitzer ,  Oliver Haeberlen ,  Franz Hirler ,  Markus Zundel ,  Rudolf Zelsacher ,  Erwin Bacher

IPC分类号： H01L21/283

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397

摘要： A method for producing a connection electrode for a first semiconductor zone and a second semiconductor zone includes producing a trench extending through the first semiconductor zone right into the second semiconductor zone in such a way that the first semiconductor zone is uncovered at sidewalls of the trench and the second semiconductor zone is uncovered at least at a bottom of the trench. The method also includes applying a protective layer to a first one of the first and second semiconductor zones in the trench, and producing a first connection zone in the second of the two semiconductor zones, which is not covered by the protective layer. The method further includes depositing an electrode layer at least onto the sidewalls and the bottom of the trench for the purpose of producing the connection electrode.

摘要翻译： 一种用于制造用于第一半导体区和第二半导体区的连接电极的方法包括制造在第二半导体区内延伸通过第一半导体区的沟槽，使得第一半导体区未被覆盖在沟槽的侧壁处， 至少在沟槽的底部露出第二半导体区域。 该方法还包括向沟槽中的第一和第二半导体区域中的第一个施加保护层，并且在两个半导体区域中的第二个半导体区域中产生未被保护层覆盖的第一连接区域。 该方法还包括至少将电极层沉积到沟槽的侧壁和底部上，以产生连接电极。

公开(公告)号：US07843006B2

公开(公告)日：2010-11-30

申请号：US11701248

申请日：2007-02-01

申请人： Rainald Sander ,  Markus Zundel

发明人： Rainald Sander ,  Markus Zundel

IPC分类号： H01L27/12

CPC分类号： H01L29/7813 ,  G01K3/005 ,  G01K7/226 ,  H01L29/0696 ,  H01L29/7803 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.

摘要翻译： 半导体元件布置包括功率晶体管和温度测量电路。 功率晶体管包括栅电极，源极区，漏区和体区。 身体区域布置在第一导电类型的第一半导体区域中。 温度测量电路包括温度依赖电阻器和耦合到温度依赖电阻器的评估电路。 电阻器由所述第一半导体区域的一部分形成。

公开(公告)号：US20100270620A1

公开(公告)日：2010-10-28

申请号：US12431504

申请日：2009-04-28

申请人： Donald Dibra ,  Christoph Kadow ,  Markus Zundel

发明人： Donald Dibra ,  Christoph Kadow ,  Markus Zundel

IPC分类号： H01L35/28 ,  H01L35/34

CPC分类号： H01L35/32 ,  G01K1/08 ,  G01K7/02

摘要： An embodiment of the invention relates to a Seebeck temperature difference sensor that may be formed in a trench on a semiconductor device. A portion of the sensor may be substantially surrounded by an electrically conductive shield. A plurality of junctions may be included to provide a higher Seebeck sensor voltage. The shield may be electrically coupled to a local potential, or left electrically floating. A portion of the shield may be formed as a doped well in the semiconductor substrate on which the semiconductor device is formed, or as a metal layer substantially covering the sensor. The shield may be formed as a first oxide layer on a sensor trench wall with a conductive shield formed on the first oxide layer, and a second oxide layer formed on the conductive shield. An absolute temperature sensor may be coupled in series with the Seebeck temperature difference sensor.

摘要翻译： 本发明的实施例涉及可以形成在半导体器件上的沟槽中的塞贝克温差传感器。 传感器的一部分可以被导电屏蔽件基本上包围。 可以包括多个结以提供更高的塞贝克传感器电压。 屏蔽可以电耦合到局部电位，或者电耦合到电浮置。 屏蔽的一部分可以形成为半导体器件形成的半导体衬底中的掺杂阱，或者形成为基本覆盖传感器的金属层。 屏蔽件可以形成为在传感器沟槽壁上的第一氧化物层，其中形成在第一氧化物层上的导电屏蔽层和形成在导电屏蔽上的第二氧化物层。 绝对温度传感器可以与塞贝克温差传感器串联耦合。

公开(公告)号：US07675114B2

公开(公告)日：2010-03-09

申请号：US11393092

申请日：2006-03-30

申请人： Markus Zundel

发明人： Markus Zundel

IPC分类号： H01L29/94 ,  H01L31/113

CPC分类号： H01L29/7813 ,  H01L29/0626 ,  H01L29/0878 ,  H01L29/42368

摘要： In order to obtain an increased avalanche strength, a trench transistor is proposed in which the breakdown location is defined in a trench bottom region below body contact zones. This is done by means of a modulation of the dopant concentration in a drift zone and an insulation layer thickness modulation in the bottom region of the trenches.

摘要翻译： 为了获得增加的雪崩强度，提出了一种沟槽晶体管，其中击穿位置被限定在主体接触区域下方的沟槽底部区域中。 这通过调制漂移区中的掺杂剂浓度和在沟槽的底部区域中的绝缘层厚度调制来完成。

公开(公告)号：US07655975B2

公开(公告)日：2010-02-02

申请号：US11264756

申请日：2005-10-31

申请人： Franz Hirler ,  Wolfgang Werner ,  Markus Zundel ,  Frank Pfirsch

发明人： Franz Hirler ,  Wolfgang Werner ,  Markus Zundel ,  Frank Pfirsch

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7813

摘要： A power trench transistor comprises a semiconductor body in which a cell array and an edge region surrounding the cell array are formed. First edge trenches are formed within the edge region. The first edge trenches contain field electrodes and the longitudinal orientations of the first edge trenches run from the cell array towards the edge of the trench transistor.

摘要翻译： 功率沟槽晶体管包括其中形成有单元阵列和围绕单元阵列的边缘区域的半导体本体。 第一边缘沟槽形成在边缘区域内。 第一边缘沟槽包含场电极，并且第一边缘沟槽的纵向取向从单元阵列朝向沟槽晶体管的边缘延伸。

公开(公告)号：US07612408B2

公开(公告)日：2009-11-03

申请号：US10996849

申请日：2004-11-24

申请人： Markus Zundel ,  Rudolf Zelsacher ,  Hermann Peri ,  Dietmar Kotz

发明人： Markus Zundel ,  Rudolf Zelsacher ,  Hermann Peri ,  Dietmar Kotz

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368

摘要： The invention relates to a MOS transistor device of the trench type, in which, in a semiconductor region of a first conductivity type, within a deep gate trench extending in the vertical direction of the semiconductor region, a vertical gate electrode and a gate oxide with a field plate step insulating the latter are formed and, in an adjoining mesa region outside and laterally with respect to the deep trench, at the upper section thereof, a source electrode region of the first conductivity type and a body region of a second conductivity type with one or a plurality of assigned body contact are formed, a drain electrode region of the first conductivity type lying opposite the deep trench in the vertical direction. The MOS transistor has a deep body reinforcement of the second conductivity type below the body region at the location of the body contact, said body reinforcement lying deeper than the field plate step.

摘要翻译： 本发明涉及一种沟槽型的MOS晶体管器件，其中在第一导电类型的半导体区域内，沿着半导体区域的垂直方向延伸的深栅极沟槽内的垂直栅电极和栅极氧化物 形成绝缘后的场板台阶，并且在其相对于深沟槽的外侧和横向相邻的台面区域的上部形成有第一导电类型的源电极区域和第二导电类型的体区域 其中形成有一个或多个分配的身体接触，所述第一导电类型的漏电极区域在垂直方向上与所述深沟槽相对。 MOS晶体管在身体接触位置处具有在身体区域下方的第二导电类型的深体增强，所述主体加强物比现场板台阶更深。

公开(公告)号：US07439579B2

公开(公告)日：2008-10-21

申请号：US11137942

申请日：2005-05-26

申请人： Rainald Sander ,  Markus Zundel

发明人： Rainald Sander ,  Markus Zundel

IPC分类号： H01L29/94

CPC分类号： H01L29/7813 ,  H01L27/0211 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/7803

摘要： A trench transistor is described. In one aspect, the trench transistor has a cell array having a plurality of cell array trenches and a plurality of mesa zones arranged between the cell array trenches, and a semiconductor functional element formed in one of the mesa zones. A current flow guiding structure is provided in the mesa zone in which the semiconductor functional element is formed, said structure being formed at least partly below the semiconductor functional element and being configured such that vertically oriented current flows out of the semiconductor functional element or into the semiconductor functional element are made more difficult and horizontally oriented current flows through the semiconductor functional element are promoted.

摘要翻译： 描述了沟槽晶体管。 在一个方面，沟槽晶体管具有具有多个单元阵列沟槽的单元阵列和布置在单元阵列沟槽之间的多个台面区，以及形成在台面区之一中的半导体功能元件。 电流引导结构设置在其中形成有半导体功能元件的台面区域中，所述结构至少部分地形成在半导体功能元件下方，并且被配置为使得垂直取向的电流流出半导体功能元件或者形成为 使半导体功能元件变得更加困难，并促进流过半导体功能元件的水平取向的电流。

公开(公告)号：US20080121991A1

公开(公告)日：2008-05-29

申请号：US11771375

申请日：2007-06-29

申请人： Markus Zundel ,  Norbert Krischke

发明人： Markus Zundel ,  Norbert Krischke

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/26586 ,  H01L21/823487 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor component arrangement and method for producing thereof is disclosed. One embodiment provides at least one power semiconductor component integrated in a semiconductor body and at least one logic component integrated in the semiconductor body. The logic component includes a trench extending into the semiconductor body proceeding from a first side, at least one gate electrode arranged in the trench and insulated from the semiconductor body by a gate dielectric, and at least one source zone and at least one drain zone of a first conduction type, which are formed in the semiconductor body in a manner adjacent to the gate dielectric and in a manner spaced apart from one another in a peripheral direction of the trench and between which at least one body zone of a second conduction type is arranged.

摘要翻译： 公开了一种半导体元件布置及其制造方法。 一个实施例提供集成在半导体本体中的至少一个功率半导体元件和集成在半导体本体中的至少一个逻辑元件。 逻辑部件包括从第一侧延伸到半导体本体中的沟槽，布置在沟槽中的至少一个栅极电极，并通过栅极电介质与半导体本体绝缘，以及至少一个源极区和至少一个漏极区 第一导电类型，其以与栅极电介质相邻的方式形成在半导体本体中，并且在沟槽的周向方向上彼此间隔开，并且其中至少一个第二导电类型的体区是 安排。

公开(公告)号：US20080076222A1

公开(公告)日：2008-03-27

申请号：US11861900

申请日：2007-09-26

申请人： Markus Zundel ,  Joachim Krumrey

发明人： Markus Zundel ,  Joachim Krumrey

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7809 ,  H01L29/7811

摘要： A method for producing an integrated circuit including a semiconductor and in one embodiment a trench transistor structure, is disclosed. A first diffusion method is carried out. A second diffusion method is carried out, by which dopant atoms of a second conduction type are introduced via a first side into a mesa region and into a component region, which form a source zone in the mesa region, the diffusion methods being coordinated with one another in such a way that the dopant atoms of a second conduction type indiffuse further than the dopant atoms of a first conduction type from the first diffusion method, in the vertical direction in the component region and indiffuse not as far as the dopant atoms of the first conduction type in the vertical direction in the mesa region.

摘要翻译： 公开了一种用于制造包括半导体并且在一个实施例中的沟槽晶体管结构的集成电路的方法。 进行第一种扩散方法。 进行第二扩散方法，通过该第二扩散方法，将第二导电类型的掺杂剂原子经由第一侧引入台面区域并形成在台面区域中形成源极区域的成分区域，扩散方法与一个 另一种方式是使得第二导电类型的掺杂剂原子比来自第一扩散方法的第一导电类型的掺杂剂原子在分量区域的垂直方向上不扩散，并且不像在 第一导电类型在台面区域的垂直方向。