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138 条记录 (耗时 0.042 秒)

    Circuit structure with low dielectric constant regions
    93.
    发明授权
    Circuit structure with low dielectric constant regions 有权
    具有低介电常数区域的电路结构

    公开(公告)号：US08772941B2

    公开(公告)日：2014-07-08

    申请号：US12206314

    申请日：2008-09-08

    申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

    发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

    IPC分类号： H01L23/522

    CPC分类号： H01L21/76808 ,  H01L21/7682

    摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

    摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

    Sidewall image transfer process employing a cap material layer for a metal nitride layer
    96.
    发明授权
    Sidewall image transfer process employing a cap material layer for a metal nitride layer 失效
    侧壁图像转印工艺采用金属氮化物层的盖材料层

    公开(公告)号：US08298954B1

    公开(公告)日：2012-10-30

    申请号：US13102224

    申请日：2011-05-06

    申请人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  David V. Horak ,  Yunpeng Yin

    发明人： John C. Arnold ,  Sean D. Burns ,  Matthew E. Colburn ,  David V. Horak ,  Yunpeng Yin

    IPC分类号： H01L21/311 ,  H01L21/302

    CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76885

    摘要： A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.

    摘要翻译： 盖材料层沉积在金属氮化物层上。 在盖材料层上形成抗反射涂层（ARC）层，有机平面化层（OPL）和图案化的线结构。 图案线结构中的图案被转移到ARC层和OPL中。 与图案化线结构和ARC层的蚀刻去除同时蚀刻盖材料层的暴露部分。 采用OPL来蚀刻金属氮化物层。 位于金属氮化物层之上的图案化盖材料层保护金属氮化物层的顶表面，并且能够在没有图案变形的情况下实现金属氮化物层中的图案的高保真度再现。 随后将金属氮化物层用作用于图案转移到下层中的蚀刻掩模。

    Dual exposure track only pitch split process
    98.
    发明授权
    Dual exposure track only pitch split process 有权
    双曝光轨道只有音高分割过程

    公开(公告)号：US07994060B2

    公开(公告)日：2011-08-09

    申请号：US12551801

    申请日：2009-09-01

    申请人： Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes

    发明人： Sean D. Burns ,  Matthew E. Colburn ,  Steven J. Holmes

    IPC分类号： H01L21/311 ,  H01L21/469

    CPC分类号： H01L21/31144 ,  G03F7/0035 ,  H01L21/0271 ,  H01L21/0338

    摘要： An integrated circuit is formed with structures spaced more closely together than a transverse dimension of such structures, such as for making contacts to electronic elements formed at minimum lithographically resolvable dimensions by dark field split pitch techniques. Acceptable overlay accuracy and process efficiency and throughput for the split pitch process that requires etching of a hard mark for each of a plurality of sequentially applied and patterned resist layers is supported by performing the etching of the hard mask entirely within a lithography track through using an acid sensitive hard mark material and an acidic overcoat which contacts areas of the hard mask through patterned apertures in the resist. The contacted areas of the hard mask are activated for development by baking of the acidic overcoat.

    摘要翻译： 集成电路形成为具有比这种结构的横向尺寸更紧密地在一起的结构，例如用于通过暗场分割俯仰技术以最小可光滑分辨尺寸形成的电子元件的接触。 对于需要蚀刻多个顺序施加的和图案化的抗蚀剂层中的每一个的硬标记的分割间距处理的可接受的覆盖精度和处理效率和处理量通过使用 酸敏感的硬标记材料和通过抗蚀剂中的图案化孔接触硬掩模的区域的酸性外涂层。 通过烘烤酸性外涂层来激活硬掩模的接触区域以进行显影。