公开(公告)号：US06284600B1

公开(公告)日：2001-09-04

申请号：US09609468

申请日：2000-07-03

申请人： Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

发明人： Yider Wu ,  Mark T. Ramsbey ,  Chi Chang ,  Yu Sun ,  Tuan Duc Pham ,  Jean Y. Yang

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

摘要翻译： 将诸如氮的预定物质放置在闪存存储器件的控制电介质结构的位线结和电介质层之间的界面处，以通过在编程或擦除操作期间最小化界面缺陷的形成来最小化这种界面的劣化 闪存设备。 将诸如氮的预定物质注入到闪速存储器件的位线结中。 执行加热半导体晶片的热处理，使得在热处理期间注入到半导体晶片内的预定物质例如氮漂移到位线结与控制电介质结构之间的界面。 在闪存器件的编程或擦除操作期间，预定种类例如接口处的氮使界面缺陷的形成最小化，从而使界面的时效性降低。

公开(公告)号：US6001713A

公开(公告)日：1999-12-14

申请号：US154074

申请日：1998-09-16

申请人： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

发明人： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

IPC分类号： H01L21/28 ,  H01L21/265

CPC分类号： H01L21/28273

摘要： Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.

摘要翻译： 提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。 该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。 所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。 这在浮动栅极内形成初始氮浓度分布。 然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。 浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。 因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。 已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。 与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。 因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

公开(公告)号：US5933730A

公开(公告)日：1999-08-03

申请号：US813562

申请日：1997-03-07

申请人： Yu Sun ,  Chi Chang ,  Mark T. Ramsbey

发明人： Yu Sun ,  Chi Chang ,  Mark T. Ramsbey

IPC分类号： H01L21/8247 ,  H01L27/105

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

摘要翻译： 本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。 该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。 根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

公开(公告)号：US5805502A

公开(公告)日：1998-09-08

申请号：US795024

申请日：1997-02-04

申请人： Yuan Tang ,  Chi Chang ,  James C. Yu

发明人： Yuan Tang ,  Chi Chang ,  James C. Yu

IPC分类号： G11C16/14 ,  G11C13/00

CPC分类号： G11C16/14

摘要： A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.

摘要翻译： 公开了根据本发明的闪存EPROM单元，其中擦除在恒定电场下完成。 FLASH EPROM单元包括包括源极，漏极和栅极的半导体器件以及耦合到源极的恒流电路。 恒流电路确保在其擦除期间将恒定场施加到FLASH EPROM单元的隧道氧化物。 在这样做时，可以以最小的压力擦除FLASH EPROM单元。 此外，本发明的FLASH EPROM单元可以与各种电源一起使用而不影响其特性。 最后，通过本发明的FLASH EPROM单元，可以显着地减少与较小设备尺寸相关的短信道效应。

公开(公告)号：US08295455B2

公开(公告)日：2012-10-23

申请号：US11756797

申请日：2007-06-01

申请人： Chi Chang

发明人： Chi Chang

IPC分类号： H04M11/00

CPC分类号： H04M1/2473 ,  G06F3/021 ,  G06F3/023 ,  G06F3/0489

摘要： A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.

摘要翻译： 包括电话功能的计算机系统。 计算机系统包括第一键盘和第一显示器。 计算机系统还包括具有至少第一功能单元和第二功能单元的处理器，并且还包括电话部分。 计算机系统可以在第一模式，第二模式或第三模式中操作。 在第一模式中，只有手机部分被激活。 在第二模式中，处理器的电话部分和第一功能单元被激活。 在第三模式中，电话部分，第一功能单元和第二功能单元中的每一个被激活。

公开(公告)号：US07958383B2

公开(公告)日：2011-06-07

申请号：US12191411

申请日：2008-08-14

申请人： Chien-Ping Chung ,  Cheng-Wei Huang ,  Chi Chang

发明人： Chien-Ping Chung ,  Cheng-Wei Huang ,  Chi Chang

IPC分类号： G06F1/04 ,  G06F5/06 ,  G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/126 ,  Y02D10/151

摘要： A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power management control signal issued by the core logic chip. For adjusting data transmission rate between the CPU and the core logic chip, a change of an asserted time of the power management control signal from a first time period to a second time period is first determined to obtain an index value. The data transmission rate is increased or decreased according to the index value.

摘要翻译： 计算机系统具有在CPU和其核心逻辑芯片之间的可调数据传输速率。 在计算机系统中，CPU具有响应于由核心逻辑芯片发出的功率管理控制信号而调整的功率状态。 为了调整CPU和核心逻辑芯片之间的数据传输速率，首先确定功率管理控制信号从第一时间段到第二时间段的断言时间的改变以获得索引值。 数据传输速率根据指标值增减。

公开(公告)号：US07785965B2

公开(公告)日：2010-08-31

申请号：US11530145

申请日：2006-09-08

申请人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

发明人： Unsoon Kim ,  Kyunghoon Min ,  Ning Cheng ,  Hiroyuki Kinoshita ,  Sugino Rinji ,  Timothy Thurgate ,  Angela Hui ,  Jihwan Choi ,  Chi Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/7923

摘要： Dual storage node memory devices and methods for fabricating dual storage node memory devices have been provided. In accordance with an exemplary embodiment, a method includes the steps of etching a plurality of trenches in a semiconductor substrate and forming a layered structure within the trenches. The layered structure includes a tunnel dielectric layer and a charge storage layer. Bit lines are formed within the semiconductor substrate and a layer of conductive material is deposited overlying the layered structure.

摘要翻译： 已经提供了双存储节点存储器件和用于制造双存储节点存储器件的方法。 根据示例性实施例，一种方法包括以下步骤：蚀刻半导体衬底中的多个沟槽并在沟槽内形成分层结构。 层状结构包括隧道介电层和电荷存储层。 位线形成在半导体衬底内，并且一层导电材料沉积在层叠结构之上。

公开(公告)号：US07643594B2

公开(公告)日：2010-01-05

申请号：US12273230

申请日：2008-11-18

申请人： Chi Chang ,  Shuyu Lin

发明人： Chi Chang ,  Shuyu Lin

IPC分类号： H04L7/00

CPC分类号： H04L7/02

摘要： A method for extracting a clock in a clock data recovery system is provided. The method includes following steps. First, a serial link transmission data is sampled for a number of times, and a number of pulse signals are generated and sequentially arranged. Then, a mark is inserted after all pulse signals are generated and had been delayed for a predetermined delay time. The predetermined delay time is less than a period between two adjacent pulse signals, and a period between two adjacent pulse signals is divided into two sub-periods by the predetermined delay time. Then, it is checked whether the data status in each sub-period is changed or not, and this operation is repeated for a predetermined number of times. Finally, the clock is extracted when a pulse signal of no data status change within the predetermined number of times is being generated.

摘要翻译： 提供了一种在时钟数据恢复系统中提取时钟的方法。 该方法包括以下步骤。 首先，对串行链路发送数据进行多次采样，生成并顺序排列多个脉冲信号。 然后，在产生所有脉冲信号之后插入一个标记，并将其延迟预定的延迟时间。 预定的延迟时间小于两个相邻脉冲信号之间的周期，并且两个相邻脉冲信号之间的周期被划分为两个子周期预定的延迟时间。 然后，检查每个子周期中的数据状态是否改变，并且该操作重复预定次数。 最后，当在预定次数内产生无数据状态改变的脉冲信号时，提取时钟。

公开(公告)号：US20090248965A1

公开(公告)日：2009-10-01

申请号：US12401466

申请日：2009-03-10

申请人： Yuan-Huei Lee ,  Chi Chang ,  Chia-Hsin Chen ,  Ming-Che Liu

发明人： Yuan-Huei Lee ,  Chi Chang ,  Chia-Hsin Chen ,  Ming-Che Liu

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7208

摘要： A hybrid flash memory device and a control method of the hybrid flash memory device are provided. The hybrid flash memory device includes a micro controller connected to a host bus for receiving data to be written in the hybrid flash memory device from a host via the host bus; and a memory module coupled to the micro controller. The flash module includes a first type of flash memory and a second type of flash memory. The data are determined to be written in a first log block of the first type of flash memory when the data size is not greater than a predetermined data size. On the contrary, the data are determined to be written in a second log block of the second type of flash memory when the data size is greater than the predetermined data size.

摘要翻译： 提供一种混合式闪速存储装置和混合式闪速存储装置的控制方法。 混合式闪速存储装置包括连接到主机总线的微控制器，用于经由主机总线从主机接收要写入混合式闪速存储器装置的数据; 以及耦合到所述微控制器的存储器模块。 闪存模块包括第一类型的闪存和第二类闪存。 当数据大小不大于预定数据大小时，数据被确定为被写入第一类闪速存储器的第一对数块中。 相反，当数据大小大于预定数据大小时，确定数据被写入第二类闪存的第二对数块中。

公开(公告)号：US07573759B2

公开(公告)日：2009-08-11

申请号：US11528639

申请日：2006-09-28

申请人： Bo-Wei Hsieh ,  Ming-Shi Liou ,  Weber Chuang ,  Chi Chang

发明人： Bo-Wei Hsieh ,  Ming-Shi Liou ,  Weber Chuang ,  Chi Chang

IPC分类号： G11C7/00

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2254

摘要： A method for detecting the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). The method executes a data reading process at first and records the latency period of the data read process to be a basis for detecting the arrival timing of the preamble in the data strobe signals in the subsequent data reading process.

摘要翻译： 一种用于从双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）检测数据选通信号的方法。 该方法首先执行数据读取处理，并将数据读取处理的等待时间周期记录为后续数据读取处理中的数据选通信号中的前导码的到达定时的基础。