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    MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
    92.
    发明申请
    MEMORY DEVICES FOR MULTIPLE READ OPERATIONS 有权

    公开(公告)号：US20250029641A1

    公开(公告)日：2025-01-23

    申请号：US18910412

    申请日：2024-10-09

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. MCNeil ,  Jung-Sheng Hoei

    IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

    Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

    TWO-TIER DEFECT SCAN MANAGEMENT
    93.
    发明申请
    TWO-TIER DEFECT SCAN MANAGEMENT 有权

    公开(公告)号：US20240402922A1

    公开(公告)日：2024-12-05

    申请号：US18806444

    申请日：2024-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

    IPC: G06F3/06

    Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

    Data burst suspend mode using multi-level signaling
    94.
    发明授权
    Data burst suspend mode using multi-level signaling 有权

    公开(公告)号：US12111781B2

    公开(公告)日：2024-10-08

    申请号：US18119576

    申请日：2023-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

    IPC: G06F13/30 ,  G06F13/16

    CPC classification number: G06F13/30 ,  G06F13/1668

    Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data burst to be initiated by toggling a logical level of a control pin from a first level corresponding to a data burst inactive mode to a second level corresponding to a data burst active mode, wherein the data burst corresponds to a data transfer across an interface bus, causing the data burst to be suspended by toggling the logical level of the control pin from the second level to a third level corresponding to a data burst suspend mode, and causing the data burst to be resumed by toggling the logical level of the control pin from the third level to the second level.

    Second read initialization on latch-limited memory device
    95.
    发明授权
    Second read initialization on latch-limited memory device 有权

    公开(公告)号：US12061806B2

    公开(公告)日：2024-08-13

    申请号：US17858778

    申请日：2022-07-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Sundararajan Sankaranarayanan ,  Eric N. Lee

    IPC: G06F3/06

    CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

    Abstract: A second read command to read second data from an array of memory cells is detected. An initial voltage to be applied to at least one wordline coupled to at least a subset of the array of memory cells is caused prior to releasing a first data associated with a first read command stored in a page buffer. The initial voltage to increase to a target value is caused. The page buffer to sense the second data from a bitline coupled to a page of the subset of the array of memory cells is caused. The sensed second data out of the bitline into the page buffer is read responsive to determining that the first data has been released from the page buffer.

    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL
    96.
    发明公开
    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL 审中-公开

    公开(公告)号：US20240231675A1

    公开(公告)日：2024-07-11

    申请号：US18611094

    申请日：2024-03-20

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Dheeraj Srinivasan

    IPC: G06F3/06

    CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0673

    Abstract: A memory system includes a ready busy pin coupled with a plurality of dice and a processing device coupled with the ready busy pin. The processing device is to perform controller operations including waiting to perform any status checks until after assertion of a pulse on a status indicator signal received from the ready busy pin; detecting the pulse being asserted is an extended pulse comprising at least a partial overlap of a first pulse asserted by a first die and a second pulse asserted by a second die of the plurality of dice; initiating a polling delay period in response to detecting assertion of the extended pulse, wherein the polling delay period is greater than a pulse width of the first pulse; and initiating a first status check of dice operations being performed by the plurality of dice in response to detecting expiration of the polling delay period.

    PROGRAM REFRESH WITH GATE-INDUCED DRAIN LEAKAGE
    98.
    发明公开
    PROGRAM REFRESH WITH GATE-INDUCED DRAIN LEAKAGE 审中-公开

    公开(公告)号：US20240038316A1

    公开(公告)日：2024-02-01

    申请号：US18223298

    申请日：2023-07-18

    Applicant: Micron Technology, Inc.

    Inventor： Huai-Yuan Tseng ,  Eric N. Lee ,  Akira Goda ,  Kishore Kumar Muchherla ,  Tomoharu Tanaka

    IPC: G11C29/12

    CPC classification number: G11C29/12005 ,  G11C2029/1202 ,  G11C2029/1204

    Abstract: A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.

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