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公开(公告)号：US11120885B2
公开(公告)日：2021-09-14
申请号：US17100582
申请日：2020-11-20
Applicant: Micron Technology, Inc.
Inventor： Michael G. Miller , Kishore Kumar Muchherla , Harish R. Singidi , Walter Di Francesco , Renato C. Padilla , Gary F. Besinga , Violante Moschiano
Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.
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公开(公告)号：US20210264991A1
公开(公告)日：2021-08-26
申请号：US17318603
申请日：2021-05-12
Applicant: Micron Technology, Inc.
Inventor： Harish Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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公开(公告)号：US11031089B2
公开(公告)日：2021-06-08
申请号：US16920154
申请日：2020-07-02
Applicant: Micron Technology, Inc.
Inventor： Harish Reddy Singidi , Kishore Kumar Muchherla , Gianni Stephen Alsasua , Ashutosh Malshe , Sampath Ratnam , Gary F. Besinga , Michael G. Miller
Abstract: Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.
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公开(公告)号：US10949344B2
公开(公告)日：2021-03-16
申请号：US16413821
申请日：2019-05-16
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Sampath K. Ratnam , Peter Feeley , Michael G. Miller , Daniel J. Hubbard , Renato C. Padilla , Ashutosh Malshe , Harish R. Singidi
Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
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公开(公告)号：US10818361B2
公开(公告)日：2020-10-27
申请号：US16381682
申请日：2019-04-11
Applicant: Micron Technology, Inc.
Inventor： Ashutosh Malshe , Harish Reddy Singidi , Kishore Kumar Muchherla , Michael G. Miller , Sampath Ratnam , Xu Zhang , Jie Zhou
Abstract: Devices and techniques for initiating and controlling preemptive idle time read scans in a flash based storage system are disclosed. In an example, a memory device includes a NAND memory array and a memory controller to schedule and initiate read scans among multiple locations of the memory array, with such read scans being preemptively triggered during an idle (background) state of the memory device, thus reducing host latency during read and write operations in an active (foreground) state of the memory device. In an example, the optimization technique includes scheduling a read scan operation, monitoring an active or idle state of host IO operations, and preemptively initiating the read scan operation when entering an idle state, before the read scan operation is scheduled to occur. In further examples, the read scan may preemptively occur based on time-based scheduling, frequency-based conditions, or event-driven conditions triggering the read scan.
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Patent Agency Ranking
公开(公告)号：US10770156B2
公开(公告)日：2020-09-08
申请号：US16416177
申请日：2019-05-18
Applicant: Micron Technology, Inc.
Inventor： Renato C. Padilla , Jung Sheng Hoei , Michael G. Miller , Roland J. Awusie , Sampath K. Ratnam , Kishore Kumar Muchherla , Gary F. Besinga , Ashutosh Malshe , Harish R. Singidi
Abstract: A memory device comprising a main memory and a controller operably connected to the main memory is provided. The main memory can comprise a plurality of memory addresses, each corresponding to a single one of a plurality of word lines. Each memory address can be included in a tracked subset of the plurality of memory addresses. Each tracked subset can include memory addresses corresponding to more than one of the plurality of word lines. The controller is configured to track a number of read operations for each tracked subset, and to scan, in response to the number of read operations for a first tracked subset exceeding a first threshold value, a portion of data corresponding to each word line of the first tracked subset to determine an error count corresponding to each word line of the first tracked subset.
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公开(公告)号：US10529434B2
公开(公告)日：2020-01-07
申请号：US16129497
申请日：2018-09-12
Applicant: Micron Technology, Inc.
Inventor： Michael G. Miller , Kishore Kumar Muchherla , Harish Reddy Singidi , Ting Luo , Ashutosh Malshe , Preston Thomson , Jianmin Huang
Abstract: Devices and techniques for detecting power loss in NAND memory devices are disclosed herein. A memory controller may calibrate a first read level for a first physical page of a number of physical pages from an initial first read level position to a calibrated first read level position. The first read level may be between a first threshold voltage distribution corresponding to a first logical state of the at least four logical states and a second threshold voltage distribution corresponding to a second logical state of the at least four logical states. Also, the first threshold voltage distribution may be a highest threshold voltage distribution for the first physical page. The memory controller may calibrate a second read level for the first physical page that is lower than the first read level from an initial second read level position to a calibrated first read level position. The memory controller may determine to refresh at least one logical page stored at the first physical page based at least in part on a first read level difference between the initial first read level and the calibrated first read level and a second read level difference between the initial second read level and the calibrated second read level.
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公开(公告)号：US10510422B2
公开(公告)日：2019-12-17
申请号：US16127085
申请日：2018-09-10
Applicant: Micron Technology, Inc.
Inventor： Gary F. Besinga , Peng Fei , Michael G. Miller , Roland J. Awusie , Kishore Kumar Muchherla , Renato C. Padilla , Harish R. Singidi , Jung Sheng Hoei , Gianni S. Alsasua
Abstract: Several embodiments of memory devices and systems with read level calibration are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region and calibration circuitry. The calibration circuitry is operably coupled to the at least one memory region and is configured to determine a read level offset value corresponding to a read level signal of the at least one memory region. In some embodiments, the calibration circuitry is configured to obtain the read level offset value internal to the main memory. The calibration circuitry is further configured to output the read level offset value to the controller.
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公开(公告)号：US10452282B2
公开(公告)日：2019-10-22
申请号：US15482337
申请日：2017-04-07
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Sampath K. Ratnam , Peter Feeley , Michael G. Miller , Preston A. Thomson , Renato C. Padilla , Ashutosh Malshe
Abstract: The present disclosure includes memory blocks erasable in a single level cell mode. A number of embodiments include a memory comprising a plurality of mixed mode blocks and a controller. The controller may be configured to identify a particular mixed mode block for an erase operation and, responsive to a determined intent to subsequently write the particular mixed mode block in a single level cell (SLC) mode, perform the erase operation in the SLC mode.
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公开(公告)号：US20190272098A1
公开(公告)日：2019-09-05
申请号：US16413821
申请日：2019-05-16
Applicant: Micron Technology, Inc.
Inventor： Kishore K. Muchherla , Sampath K. Ratnam , Peter Feeley , Michael G. Miller , Daniel J. Hubbard , Renato C. Padilla , Ashutosh Malshe , Harish R. Singidi
Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.
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