公开(公告)号：US20220130850A1

公开(公告)日：2022-04-28

申请号：US17647238

申请日：2022-01-06

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  John D. Hopkins ,  Roger W. Lindsay ,  Shuangqiang Luo

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11529 ,  H01L21/768

Abstract: A method of forming a microelectronic device comprises forming isolated nitride structures on steps of stair step structures comprising stacked tiers comprising alternating levels of a first insulative material and a second insulative material, forming a photoresist material over some of the stair step structures, and replacing the isolated nitride structures and the second insulative material with an electrically conductive material to respectively form conductive pad structures and electrically conductive lines. Related microelectronic devices and electronic devices are also disclosed.

公开(公告)号：US20220115335A1

公开(公告)日：2022-04-14

申请号：US17559321

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Rohit Kothari ,  Lifang Xu ,  Jian Li

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: Some embodiments include an integrated assembly having a semiconductor die with memory array regions and one or more regions peripheral to the memory array regions. A stack of alternating insulative and conductive levels extends across the memory array regions and passes into at least one of the peripheral regions. The stack generates bending stresses on the die. At least one stress-moderating region extends through the stack and is configured to alleviate the bending stresses.

公开(公告)号：US11264275B2

公开(公告)日：2022-03-01

申请号：US16872598

申请日：2020-05-12

Applicant: Micron Technology, inc.

Inventor： John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L27/11524

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210358805A1

公开(公告)日：2021-11-18

申请号：US16872598

申请日：2020-05-12

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535

Abstract: Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels contain conductive material and the second levels contain insulative material. At least some of the first and second levels are configured as steps. Each of the steps has one of the second levels over an associated one of the first levels. A layer is over the steps and is spaced from the stack by an intervening insulative region. Insulative material is over the layer. Conductive interconnects extend through the insulative material, through the layer, through the intervening insulative region and to the conductive material within the first levels of the steps. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11177278B2

公开(公告)日：2021-11-16

申请号：US16675901

申请日：2019-11-06

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Lifang Xu

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells are in the stack. The channel-material strings project upwardly from material of an uppermost of the tiers. A first insulator material is above the material of the uppermost tier directly against sides of channel material of the upwardly-projecting channel-material strings. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is above the first insulator material. The first and second insulator materials comprise different compositions relative one another. Conductive vias in the second insulator material are individually directly electrically coupled to individual of the channel-material strings. Other embodiments, including methods, are disclosed.

公开(公告)号：US11114379B2

公开(公告)日：2021-09-07

申请号：US15995475

申请日：2018-06-01

Applicant: Micron Technology, Inc.

Inventor： Michael J. Gossman ,  M. Jared Barclay ,  Matthew J. King ,  Eldon Nelson ,  Matthew Park ,  Jason Reece ,  Lifang Xu ,  Bo Zhao

IPC: H01L23/528 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11548 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11529

Abstract: A method used in forming integrated circuitry comprises forming a stack of vertically-alternating tiers of different composition materials. A stair-step structure is formed into the stack and an upper landing is formed adjacent and above the stair-step structure. The stair-step structure is formed to comprise vertically-alternating tiers of the different composition materials. A plurality of stairs individually comprise two of the tiers of different composition materials. At least some of the stairs individually have only two tiers that are each only of a different one of the different composition materials. An upper of the stairs that is below the upper landing comprises at least four of the tiers of different composition materials. Structure independent of method is disclosed.

公开(公告)号：US20210265371A1

公开(公告)日：2021-08-26

申请号：US16799543

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Nancy M. Lomeli ,  Lifang Xu

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  G11C5/06

Abstract: A microelectronic device comprises a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, the tiers individually comprising one of the conductive structures and one of the insulating structures, a staircase structure within the stack structure and having steps comprising edges of at least some of the tiers, conductive contact structures on the steps of the staircase structure, support pillar structures laterally offset in at least a first direction from the conductive contact structures and extending through the stack structure, and bridge structures comprising an electrically insulating material extending vertically through at least a portion of the stack structure and between at least some adjacent support pillar structures of the support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20210257385A1

公开(公告)日：2021-08-19

申请号：US17215308

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Yi Hu ,  Merri L. Carlson ,  Anilkumar Chandolu ,  Indra V. Chary ,  David Daycock ,  Harsh Narendrakumar Jain ,  Matthew J. King ,  Jian Li ,  Brett D. Lowe ,  Prakash Rau Mokhna Rau ,  Lifang Xu

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/3213 ,  H01L27/11556

Abstract: A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.

公开(公告)号：US20210257298A1

公开(公告)日：2021-08-19

申请号：US16790148

申请日：2020-02-13

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Jian Li ,  Graham R. Wolstenholme ,  Paolo Tessariol ,  George Matamis ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

公开(公告)号：US11088017B2

公开(公告)日：2021-08-10

申请号：US16806312

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： John B. Matovu ,  David S. Meyaard ,  Gowrisankar Damarla ,  Sri Sai Sivakumar Vegunta ,  Kunal Shrotri ,  Shashank Saraf ,  Kevin R. Gast ,  Jivaan Kishore Jhothiraman ,  Suresh Ramarajan ,  Lifang Xu ,  Rithu K. Bhonsle ,  Rutuparna Narulkar ,  Matthew J. King

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L21/3105 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11548

Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material. Related methods of forming semiconductor structures and related semiconductor devices are disclosed.